Hybrid BIST scheme for multiple heterogeneous embedded memories

Li Ming Denq, Yu Tsao Hsing, Cheng W. Wu

Research output: Contribution to journalArticle

7 Citations (Scopus)


Many embedded memories in SoCs have wide data words, leading to a high routing penalty in the BIST circuits. This novel hybrid BIST architecture reduces this routing penalty, while allowing at-speed test and diagnosis of memory cores. The MECA system facilitates mapping the diagnostic syndrome to the memory cell's defect information. A failure bitmap viewer provides visual information for design and process diagnostics.

Original languageEnglish
Pages (from-to)64-73
Number of pages10
JournalIEEE Design and Test of Computers
Issue number2
Publication statusPublished - 2009 Jun 3

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

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