Abstract
Many embedded memories in SoCs have wide data words, leading to a high routing penalty in the BIST circuits. This novel hybrid BIST architecture reduces this routing penalty, while allowing at-speed test and diagnosis of memory cores. The MECA system facilitates mapping the diagnostic syndrome to the memory cell's defect information. A failure bitmap viewer provides visual information for design and process diagnostics.
Original language | English |
---|---|
Pages (from-to) | 64-73 |
Number of pages | 10 |
Journal | IEEE Design and Test of Computers |
Volume | 26 |
Issue number | 2 |
DOIs | |
Publication status | Published - 2009 Jun 3 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Software
- Electrical and Electronic Engineering