Hybrid BIST scheme for multiple heterogeneous embedded memories

Li Ming Denq; Yu Tsao Hsing; Cheng W. Wu

doi:10.1109/MDT.2009.37

Hybrid BIST scheme for multiple heterogeneous embedded memories

Li Ming Denq, Yu Tsao Hsing, Cheng W. Wu

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

7 Citations (Scopus)

Abstract

Many embedded memories in SoCs have wide data words, leading to a high routing penalty in the BIST circuits. This novel hybrid BIST architecture reduces this routing penalty, while allowing at-speed test and diagnosis of memory cores. The MECA system facilitates mapping the diagnostic syndrome to the memory cell's defect information. A failure bitmap viewer provides visual information for design and process diagnostics.

Original language	English
Pages (from-to)	64-73
Number of pages	10
Journal	IEEE Design and Test of Computers
Volume	26
Issue number	2
DOIs	https://doi.org/10.1109/MDT.2009.37
Publication status	Published - 2009 Jun 3

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Software
Electrical and Electronic Engineering

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10.1109/MDT.2009.37

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abstract = "Many embedded memories in SoCs have wide data words, leading to a high routing penalty in the BIST circuits. This novel hybrid BIST architecture reduces this routing penalty, while allowing at-speed test and diagnosis of memory cores. The MECA system facilitates mapping the diagnostic syndrome to the memory cell's defect information. A failure bitmap viewer provides visual information for design and process diagnostics.",

author = "Denq, {Li Ming} and Hsing, {Yu Tsao} and Wu, {Cheng W.}",

note = "Funding Information: This work was supported in part by the National Science Council, Taiwan, under contract NSC 95-2220-E-007-021, and the Ministry of Economic Affairs, Taiwan, under contract 94-EC-17-A-01-S1-002.",

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AU - Wu, Cheng W.

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PY - 2009/6/3

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N2 - Many embedded memories in SoCs have wide data words, leading to a high routing penalty in the BIST circuits. This novel hybrid BIST architecture reduces this routing penalty, while allowing at-speed test and diagnosis of memory cores. The MECA system facilitates mapping the diagnostic syndrome to the memory cell's defect information. A failure bitmap viewer provides visual information for design and process diagnostics.

AB - Many embedded memories in SoCs have wide data words, leading to a high routing penalty in the BIST circuits. This novel hybrid BIST architecture reduces this routing penalty, while allowing at-speed test and diagnosis of memory cores. The MECA system facilitates mapping the diagnostic syndrome to the memory cell's defect information. A failure bitmap viewer provides visual information for design and process diagnostics.

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Hybrid BIST scheme for multiple heterogeneous embedded memories

Abstract

All Science Journal Classification (ASJC) codes

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