Impact of High-K Offset Spacer in 65-nm Node SOI Devices

Ming Wen Ma, Tan Fu Lei, Chien Hung Wu, Shui Jinn Wang, Tsung Yu Yang, Kuo Hsing Kao, Woei Cherng Wu, Tien Sheng Chao

Research output: Contribution to journalArticlepeer-review

24 Citations (Scopus)


In this letter, 65-nm node silicon-on-insulator devices with high-k offset spacer dielectric were investigated by extensive 2-D device simulation. The result shows that the high-k offset spacer dielectric can effectively increase the ON-state driving current Ion and reduce the off leakage current ioffdue to the high vertical fringing electric field effect. This fringing field can significantly improve the ion/ioffcurrent ratio and the subthreshold swing compared with the conventional oxide spacer. Consequently, the gate-to-channel control ability is enhanced by the fringing field via the high-k offset spacer dielectric.

Original languageEnglish
Pages (from-to)238-241
Number of pages4
JournalIEEE Electron Device Letters
Issue number3
Publication statusPublished - 2007 Mar 7

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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