TY - GEN
T1 - Impacts of high-κ offset spacer on 65-nm node SOI devices
AU - Ma, Ming Wen
AU - Chao, Tien Sheng
AU - Kao, Kuo-Hsing
AU - Huang, Jyun Siang
AU - Lei, Tan Fu
PY - 2006/12/12
Y1 - 2006/12/12
N2 - In this paper, the 65 -nm node SOI devices with high-K offset spacer dielectric was investigated by a two-dimensional device simulation. Calculated results show that the high-K offset spacer dielectric can effectively increase the on-state driving current Ion and reduce the off-state leakage current I off due to the high vertical fringing electric field effect arising from the side capacitor comprising of gate/offset spacer/drain extension structure. This fringing field and, in turn, the Ion/Ioff current ratio and subthreshold swing can be strongly enhanced by increasing the dielectric constant of the offset spacer.
AB - In this paper, the 65 -nm node SOI devices with high-K offset spacer dielectric was investigated by a two-dimensional device simulation. Calculated results show that the high-K offset spacer dielectric can effectively increase the on-state driving current Ion and reduce the off-state leakage current I off due to the high vertical fringing electric field effect arising from the side capacitor comprising of gate/offset spacer/drain extension structure. This fringing field and, in turn, the Ion/Ioff current ratio and subthreshold swing can be strongly enhanced by increasing the dielectric constant of the offset spacer.
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M3 - Conference contribution
AN - SCOPUS:33845335869
SN - 0976798565
SN - 9780976798569
T3 - 2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings
SP - 697
EP - 700
BT - 2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings
T2 - 2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings
Y2 - 7 May 2006 through 11 May 2006
ER -