Impacts of high-κ offset spacer on 65-nm node SOI devices

In this paper, the 65 -nm node SOI devices with high-K offset spacer dielectric was investigated by a two-dimensional device simulation. Calculated results show that the high-K offset spacer dielectric can effectively increase the on-state driving current Ion and reduce the off-state leakage current I _off due to the high vertical fringing electric field effect arising from the side capacitor comprising of gate/offset spacer/drain extension structure. This fringing field and, in turn, the I_on/I_off current ratio and subthreshold swing can be strongly enhanced by increasing the dielectric constant of the offset spacer.