Improved high-k stacks with chemical oxide interfacial layer by DPN/PNA treatment

Shuguang Li; Ying Tsung Chen; Shoou Jinn Chang

doi:10.1016/j.cap.2014.12.010

Improved high-k stacks with chemical oxide interfacial layer by DPN/PNA treatment

Shuguang Li, Ying Tsung Chen, Shoou Jinn Chang

Research output: Contribution to journal › Article › peer-review

Abstract

A decoupled plasma nitridation (DPN) with post nitridation annealing (PNA) treatment method was introduced to improve the performances of MOS devices with high-k (HK)-last/gate-last integration scheme and chemical oxide interface layer (IL). By introducing N to form HfSiON, it was found that DPN + PNA treatments could provide smaller equivalent oxide thickness (EOT) for both nMOS and pMOS devices. It was also found that we could achieve the best overall device performance for the HK-last/gatelast integration scheme with a chemical oxide IL by introducing nitrogen gas with low percentage content during DPN followed by high temperature PNA.

Original language	English
Pages (from-to)	180-182
Number of pages	3
Journal	Current Applied Physics
Volume	15
Issue number	3
DOIs	https://doi.org/10.1016/j.cap.2014.12.010
Publication status	Published - 2015 Mar

All Science Journal Classification (ASJC) codes

Materials Science(all)
Physics and Astronomy(all)

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title = "Improved high-k stacks with chemical oxide interfacial layer by DPN/PNA treatment",

abstract = "A decoupled plasma nitridation (DPN) with post nitridation annealing (PNA) treatment method was introduced to improve the performances of MOS devices with high-k (HK)-last/gate-last integration scheme and chemical oxide interface layer (IL). By introducing N to form HfSiON, it was found that DPN + PNA treatments could provide smaller equivalent oxide thickness (EOT) for both nMOS and pMOS devices. It was also found that we could achieve the best overall device performance for the HK-last/gatelast integration scheme with a chemical oxide IL by introducing nitrogen gas with low percentage content during DPN followed by high temperature PNA.",

author = "Shuguang Li and Chen, {Ying Tsung} and Chang, {Shoou Jinn}",

year = "2015",

month = mar,

doi = "10.1016/j.cap.2014.12.010",

language = "English",

volume = "15",

pages = "180--182",

journal = "Current Applied Physics",

issn = "1567-1739",

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AB - A decoupled plasma nitridation (DPN) with post nitridation annealing (PNA) treatment method was introduced to improve the performances of MOS devices with high-k (HK)-last/gate-last integration scheme and chemical oxide interface layer (IL). By introducing N to form HfSiON, it was found that DPN + PNA treatments could provide smaller equivalent oxide thickness (EOT) for both nMOS and pMOS devices. It was also found that we could achieve the best overall device performance for the HK-last/gatelast integration scheme with a chemical oxide IL by introducing nitrogen gas with low percentage content during DPN followed by high temperature PNA.

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