Improved poly gate engineering for 65 nm low power CMOS technology

Chan Yuan Hu, Jone F. Chen, Shih Chih Chen, Shoou Jinn Chang, Chih Ping Lee, T. H. Lee

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)


A design for the polycrystalline gate is developed for 65 nm low power complementary metal oxide semiconductor (CMOS) technology. Using the poly deposition, a less poly depletion effect and a decrease in the electrical gate dielectric thickness (Tox) can be obtained. Also, the poly deposition successfully reduces the roughness of the poly surface and produces a smaller poly grain size after subsequent rapid thermal processing steps. Meanwhile, the poly deposition can suppress the short channel effect and can reduce off-state leakage current. The poly deposition results in better voltage ramp dielectric breakdown and uniformity on a specific test vehicle. The Idsat asymmetry characteristics of the device are also improved by the poly deposition. The Vcc-min of the 0.525 μ m2 cell size 6T-static random access memory using the poly deposition is also improved due to leakage current reduction and well Idsat asymmetry.

Original languageEnglish
Pages (from-to)H38-H43
JournalJournal of the Electrochemical Society
Issue number1
Publication statusPublished - 2010

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Renewable Energy, Sustainability and the Environment
  • Surfaces, Coatings and Films
  • Electrochemistry
  • Materials Chemistry


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