Improved poly gate engineering for 65 nm low power CMOS technology

Chan Yuan Hu, Jone-Fang Chen, Shih Chih Chen, Shoou-Jinn Chang, Chih Ping Lee, T. H. Lee

Research output: Contribution to journalArticle

Abstract

A design for the polycrystalline gate is developed for 65 nm low power complementary metal oxide semiconductor (CMOS) technology. Using the poly deposition, a less poly depletion effect and a decrease in the electrical gate dielectric thickness (Tox) can be obtained. Also, the poly deposition successfully reduces the roughness of the poly surface and produces a smaller poly grain size after subsequent rapid thermal processing steps. Meanwhile, the poly deposition can suppress the short channel effect and can reduce off-state leakage current. The poly deposition results in better voltage ramp dielectric breakdown and uniformity on a specific test vehicle. The Idsat asymmetry characteristics of the device are also improved by the poly deposition. The Vcc-min of the 0.525 μ m2 cell size 6T-static random access memory using the poly deposition is also improved due to leakage current reduction and well Idsat asymmetry.

Original languageEnglish
JournalJournal of the Electrochemical Society
Volume157
Issue number1
DOIs
Publication statusPublished - 2010 Jan 1

Fingerprint

CMOS
Metals
engineering
Leakage currents
leakage
asymmetry
Rapid thermal processing
test vehicles
Gate dielectrics
random access memory
ramps
Electric breakdown
Oxide semiconductors
depletion
roughness
breakdown
grain size
Surface roughness
Data storage equipment
Electric potential

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Renewable Energy, Sustainability and the Environment
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrochemistry
  • Materials Chemistry

Cite this

Hu, Chan Yuan ; Chen, Jone-Fang ; Chen, Shih Chih ; Chang, Shoou-Jinn ; Lee, Chih Ping ; Lee, T. H. / Improved poly gate engineering for 65 nm low power CMOS technology. In: Journal of the Electrochemical Society. 2010 ; Vol. 157, No. 1.
@article{1eb8914170b946a3a2f02612f1db0ddc,
title = "Improved poly gate engineering for 65 nm low power CMOS technology",
abstract = "A design for the polycrystalline gate is developed for 65 nm low power complementary metal oxide semiconductor (CMOS) technology. Using the poly deposition, a less poly depletion effect and a decrease in the electrical gate dielectric thickness (Tox) can be obtained. Also, the poly deposition successfully reduces the roughness of the poly surface and produces a smaller poly grain size after subsequent rapid thermal processing steps. Meanwhile, the poly deposition can suppress the short channel effect and can reduce off-state leakage current. The poly deposition results in better voltage ramp dielectric breakdown and uniformity on a specific test vehicle. The Idsat asymmetry characteristics of the device are also improved by the poly deposition. The Vcc-min of the 0.525 μ m2 cell size 6T-static random access memory using the poly deposition is also improved due to leakage current reduction and well Idsat asymmetry.",
author = "Hu, {Chan Yuan} and Jone-Fang Chen and Chen, {Shih Chih} and Shoou-Jinn Chang and Lee, {Chih Ping} and Lee, {T. H.}",
year = "2010",
month = "1",
day = "1",
doi = "10.1149/1.3246796",
language = "English",
volume = "157",
journal = "Journal of the Electrochemical Society",
issn = "0013-4651",
publisher = "Electrochemical Society, Inc.",
number = "1",

}

Improved poly gate engineering for 65 nm low power CMOS technology. / Hu, Chan Yuan; Chen, Jone-Fang; Chen, Shih Chih; Chang, Shoou-Jinn; Lee, Chih Ping; Lee, T. H.

In: Journal of the Electrochemical Society, Vol. 157, No. 1, 01.01.2010.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Improved poly gate engineering for 65 nm low power CMOS technology

AU - Hu, Chan Yuan

AU - Chen, Jone-Fang

AU - Chen, Shih Chih

AU - Chang, Shoou-Jinn

AU - Lee, Chih Ping

AU - Lee, T. H.

PY - 2010/1/1

Y1 - 2010/1/1

N2 - A design for the polycrystalline gate is developed for 65 nm low power complementary metal oxide semiconductor (CMOS) technology. Using the poly deposition, a less poly depletion effect and a decrease in the electrical gate dielectric thickness (Tox) can be obtained. Also, the poly deposition successfully reduces the roughness of the poly surface and produces a smaller poly grain size after subsequent rapid thermal processing steps. Meanwhile, the poly deposition can suppress the short channel effect and can reduce off-state leakage current. The poly deposition results in better voltage ramp dielectric breakdown and uniformity on a specific test vehicle. The Idsat asymmetry characteristics of the device are also improved by the poly deposition. The Vcc-min of the 0.525 μ m2 cell size 6T-static random access memory using the poly deposition is also improved due to leakage current reduction and well Idsat asymmetry.

AB - A design for the polycrystalline gate is developed for 65 nm low power complementary metal oxide semiconductor (CMOS) technology. Using the poly deposition, a less poly depletion effect and a decrease in the electrical gate dielectric thickness (Tox) can be obtained. Also, the poly deposition successfully reduces the roughness of the poly surface and produces a smaller poly grain size after subsequent rapid thermal processing steps. Meanwhile, the poly deposition can suppress the short channel effect and can reduce off-state leakage current. The poly deposition results in better voltage ramp dielectric breakdown and uniformity on a specific test vehicle. The Idsat asymmetry characteristics of the device are also improved by the poly deposition. The Vcc-min of the 0.525 μ m2 cell size 6T-static random access memory using the poly deposition is also improved due to leakage current reduction and well Idsat asymmetry.

UR - http://www.scopus.com/inward/record.url?scp=72249110058&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=72249110058&partnerID=8YFLogxK

U2 - 10.1149/1.3246796

DO - 10.1149/1.3246796

M3 - Article

AN - SCOPUS:72249110058

VL - 157

JO - Journal of the Electrochemical Society

JF - Journal of the Electrochemical Society

SN - 0013-4651

IS - 1

ER -