Improved poly gate engineering for 65 nm low power CMOS technology

A design for the polycrystalline gate is developed for 65 nm low power complementary metal oxide semiconductor (CMOS) technology. Using the poly deposition, a less poly depletion effect and a decrease in the electrical gate dielectric thickness (T_ox) can be obtained. Also, the poly deposition successfully reduces the roughness of the poly surface and produces a smaller poly grain size after subsequent rapid thermal processing steps. Meanwhile, the poly deposition can suppress the short channel effect and can reduce off-state leakage current. The poly deposition results in better voltage ramp dielectric breakdown and uniformity on a specific test vehicle. The I_dsat asymmetry characteristics of the device are also improved by the poly deposition. The V_cc-min of the 0.525 μ m² cell size 6T-static random access memory using the poly deposition is also improved due to leakage current reduction and well I_dsat asymmetry.