Improvement of poly-pimple-induced device mismatch on 6T-SRAM at 65-nm CMOS technology

Chan Yuan Hu; Jone F. Chen; Shih Chih Chen; Shoou Jinn Chang; Kay Ming Lee; Chih Ping Lee

doi:10.1109/TED.2010.2041285

Improvement of poly-pimple-induced device mismatch on 6T-SRAM at 65-nm CMOS technology

Chan Yuan Hu, Jone F. Chen, Shih Chih Chen, Shoou Jinn Chang, Kay Ming Lee, Chih Ping Lee

Research output: Contribution to journal › Article › peer-review

Abstract

An incremental poly etching method can improve the poly pimple defect-induced device mismatch on the static noise margin (SNM) of 65-nm-node low-power 6T-SRAM. The improvement on circuit level is examined by the yield of scan chain and memory built-in self-test (MBIST), which is known to correlate well to process-induced defects.

Original language	English
Article number	5418971
Pages (from-to)	956-959
Number of pages	4
Journal	IEEE Transactions on Electron Devices
Volume	57
Issue number	4
DOIs	https://doi.org/10.1109/TED.2010.2041285
Publication status	Published - 2010 Apr

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/TED.2010.2041285

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abstract = "An incremental poly etching method can improve the poly pimple defect-induced device mismatch on the static noise margin (SNM) of 65-nm-node low-power 6T-SRAM. The improvement on circuit level is examined by the yield of scan chain and memory built-in self-test (MBIST), which is known to correlate well to process-induced defects.",

author = "Hu, {Chan Yuan} and Chen, {Jone F.} and Chen, {Shih Chih} and Chang, {Shoou Jinn} and Lee, {Kay Ming} and Lee, {Chih Ping}",

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AU - Chang, Shoou Jinn

AU - Lee, Kay Ming

AU - Lee, Chih Ping

PY - 2010/4

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Improvement of poly-pimple-induced device mismatch on 6T-SRAM at 65-nm CMOS technology

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