Improving scalability and complexity of dynamic scheduler through wakeup-based scheduling

Kuo Su Hsiao, Chung-Ho Chen

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Abstract

This paper presents a new scheduling technique to improve the speed, power, and scalability of a dynamic scheduler. In a high-performance superscalar processor, the instruction scheduler comes with poor scalability and high complexity due to the inefficient and costly instruction wakeup operation. From simulation-based analyses, we find that 98% of the wakeup activities are useless in the conventional wakeup logic. These useless activities consume a lot of power and slowdown the scheduling speed. To address this problem, the proposed technique schedules the instructions into the segmented issue window based on their wakeup addresses. During the wakeup process, the wakeup operation is only performed in the segment selected by the wakeup address of the result tag. The other segments are excluded from the wakeup operation to reduce the useless wakeup activities. The experimental results show that the proposed technique saves 50-61% of the power consumption, reduces 42-76% in the wakeup latency compared to the conventional design.

Original languageEnglish
Pages197-202
Number of pages6
DOIs
Publication statusPublished - 2006 Dec 1
Event24th International Conference on Computer Design 2006, ICCD - San Jose, CA, United States
Duration: 2006 Oct 12006 Oct 4

Other

Other24th International Conference on Computer Design 2006, ICCD
CountryUnited States
CitySan Jose, CA
Period06-10-0106-10-04

All Science Journal Classification (ASJC) codes

  • Computer Graphics and Computer-Aided Design
  • Software

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    Hsiao, K. S., & Chen, C-H. (2006). Improving scalability and complexity of dynamic scheduler through wakeup-based scheduling. 197-202. Paper presented at 24th International Conference on Computer Design 2006, ICCD, San Jose, CA, United States. https://doi.org/10.1109/ICCD.2006.4380817