Abstract
This paper presents a new scheduling technique to improve the speed, power, and scalability of a dynamic scheduler. In a high-performance superscalar processor, the instruction scheduler comes with poor scalability and high complexity due to the inefficient and costly instruction wakeup operation. From simulation-based analyses, we find that 98% of the wakeup activities are useless in the conventional wakeup logic. These useless activities consume a lot of power and slowdown the scheduling speed. To address this problem, the proposed technique schedules the instructions into the segmented issue window based on their wakeup addresses. During the wakeup process, the wakeup operation is only performed in the segment selected by the wakeup address of the result tag. The other segments are excluded from the wakeup operation to reduce the useless wakeup activities. The experimental results show that the proposed technique saves 50-61% of the power consumption, reduces 42-76% in the wakeup latency compared to the conventional design.
| Original language | English |
|---|---|
| Pages | 197-202 |
| Number of pages | 6 |
| DOIs | |
| Publication status | Published - 2006 Dec 1 |
| Event | 24th International Conference on Computer Design 2006, ICCD - San Jose, CA, United States Duration: 2006 Oct 1 → 2006 Oct 4 |
Other
| Other | 24th International Conference on Computer Design 2006, ICCD |
|---|---|
| Country | United States |
| City | San Jose, CA |
| Period | 06-10-01 → 06-10-04 |
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All Science Journal Classification (ASJC) codes
- Computer Graphics and Computer-Aided Design
- Software
Cite this
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Improving scalability and complexity of dynamic scheduler through wakeup-based scheduling. / Hsiao, Kuo Su; Chen, Chung-Ho.
2006. 197-202 Paper presented at 24th International Conference on Computer Design 2006, ICCD, San Jose, CA, United States.Research output: Contribution to conference › Paper
TY - CONF
T1 - Improving scalability and complexity of dynamic scheduler through wakeup-based scheduling
AU - Hsiao, Kuo Su
AU - Chen, Chung-Ho
PY - 2006/12/1
Y1 - 2006/12/1
N2 - This paper presents a new scheduling technique to improve the speed, power, and scalability of a dynamic scheduler. In a high-performance superscalar processor, the instruction scheduler comes with poor scalability and high complexity due to the inefficient and costly instruction wakeup operation. From simulation-based analyses, we find that 98% of the wakeup activities are useless in the conventional wakeup logic. These useless activities consume a lot of power and slowdown the scheduling speed. To address this problem, the proposed technique schedules the instructions into the segmented issue window based on their wakeup addresses. During the wakeup process, the wakeup operation is only performed in the segment selected by the wakeup address of the result tag. The other segments are excluded from the wakeup operation to reduce the useless wakeup activities. The experimental results show that the proposed technique saves 50-61% of the power consumption, reduces 42-76% in the wakeup latency compared to the conventional design.
AB - This paper presents a new scheduling technique to improve the speed, power, and scalability of a dynamic scheduler. In a high-performance superscalar processor, the instruction scheduler comes with poor scalability and high complexity due to the inefficient and costly instruction wakeup operation. From simulation-based analyses, we find that 98% of the wakeup activities are useless in the conventional wakeup logic. These useless activities consume a lot of power and slowdown the scheduling speed. To address this problem, the proposed technique schedules the instructions into the segmented issue window based on their wakeup addresses. During the wakeup process, the wakeup operation is only performed in the segment selected by the wakeup address of the result tag. The other segments are excluded from the wakeup operation to reduce the useless wakeup activities. The experimental results show that the proposed technique saves 50-61% of the power consumption, reduces 42-76% in the wakeup latency compared to the conventional design.
UR - http://www.scopus.com/inward/record.url?scp=49749102042&partnerID=8YFLogxK
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U2 - 10.1109/ICCD.2006.4380817
DO - 10.1109/ICCD.2006.4380817
M3 - Paper
SP - 197
EP - 202
ER -