TY - GEN
T1 - Improving testing and diagnosis efficiency for regular memory arrays
AU - Wu, Tsung Yu
AU - Chen, Po Yuan
AU - Wu, Cheng Wen
AU - Kwai, Ding Ming
PY - 2010/11/8
Y1 - 2010/11/8
N2 - Built-in self-test (BIST) is one of the most widely used design-for-testability (DFT) techniques, particularly for embedded random access memory (RAM). To ease the test and diagnosis flow, we have previously developed a synthesis compiler, called BRAINS which stands for BIST for RAM in Seconds. It possesses many nice features, such as accessibility, scalability, programmability, and flexibility, thereby improving the testability, yield, and reliability. However, for regular arrays, the conventional flow attaches a BIST circuit to each memory element, and scans in test patterns or performs sequential diagnosis, so is inefficient in terms of test time. In this work, we extend the BRAINS functions by taking advantage of the regular structure. With these extensions, the test and diagnosis flow becomes very simple. In the experiments on a 32-core array, the overall test time can be reduced by 6 to 23 times with only minor area overhead varying from 10% to 17%, as compared with the original BRAINS design.
AB - Built-in self-test (BIST) is one of the most widely used design-for-testability (DFT) techniques, particularly for embedded random access memory (RAM). To ease the test and diagnosis flow, we have previously developed a synthesis compiler, called BRAINS which stands for BIST for RAM in Seconds. It possesses many nice features, such as accessibility, scalability, programmability, and flexibility, thereby improving the testability, yield, and reliability. However, for regular arrays, the conventional flow attaches a BIST circuit to each memory element, and scans in test patterns or performs sequential diagnosis, so is inefficient in terms of test time. In this work, we extend the BRAINS functions by taking advantage of the regular structure. With these extensions, the test and diagnosis flow becomes very simple. In the experiments on a 32-core array, the overall test time can be reduced by 6 to 23 times with only minor area overhead varying from 10% to 17%, as compared with the original BRAINS design.
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U2 - 10.1109/VDAT.2010.5496701
DO - 10.1109/VDAT.2010.5496701
M3 - Conference contribution
AN - SCOPUS:78049404003
SN - 9781424452712
T3 - Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
SP - 100
EP - 103
BT - Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
T2 - 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
Y2 - 26 April 2010 through 29 April 2010
ER -