Infection-based dead page prediction in hybrid memory architecture

Ing Chao Lin, Da Wei Chang, Chen Tai Kao, Sheng Xuan Lin

Research output: Contribution to journalArticlepeer-review


With the widespread use of cloud computing and the Internet, applications that require a large memory footprint, such as in-memory databases, have gained in popularity. These applications depend on a high capacity, reliable memory architecture. To achieve these two goals, hybrid memory that uses both DRAM and nonvolatile memory (NVM) provides benefits that include large capacity and nonvolatility. However, NVM is usually accompanied by high write latency and endurance problems. It is important to reduce NVM writes and improve the latency and lifetime of hybrid memory. One way to reduce NVM writes is to reduce dead pages that occupy DRAM and have not been accessed for a long time. When dead pages are removed from the memory, more space can be reserved for frequently accessed data, reducing DRAM misses and NVM writes. Currently, there are several dead block prediction techniques that can identify dead blocks and reduce miss rates at the cache level. However, they are not effective at the memory level because CPU memory accesses exhibit less locality when accesses are filtered by caches. To propose an application that is suitable at the memory level and to achieve a reduction in NVM writes, this paper proposes a simple but effective dead page predictor, called the infection-based dead page predictor (IDP), for the memory level. IDP uses the access counts of evicted pages to determine if nearby pages are also dead pages (i.e., other pages are infected by evicted pages). The simulation results show that compared to related work, the proposed predictor significantly reduces DRAM misses and enhances lifetime.

Original languageEnglish
Article number8760526
Pages (from-to)2401-2412
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number10
Publication statusPublished - 2019 Oct

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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