Abstract
This work investigates the scaling impact on the feasibility of back-gate biasing for ultra-thin-body and BOX fully depleted SOI MOSFETs (UTBB FD SOI) at 5nm technology node. Though the effectiveness of the threshold voltage (Vt) modulation by back bias is limited due to bulk inversion as a result of silicon film scaling, such an issue of reduced Vt window can be relieved by decreasing BOX thickness as the back-gate coupling could be enhanced by thin-BOX-reduced inversion charge centroid in scaled SOI film.
| Original language | English |
|---|---|
| Title of host publication | 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9781538676264 |
| DOIs | |
| Publication status | Published - 2019 Feb 11 |
| Event | 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 - Burlingame, United States Duration: 2018 Oct 15 → 2018 Oct 18 |
Publication series
| Name | 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 |
|---|
Conference
| Conference | 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 |
|---|---|
| Country | United States |
| City | Burlingame |
| Period | 18-10-15 → 18-10-18 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality
- Electronic, Optical and Magnetic Materials
- Instrumentation
Cite this
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Insights to the scaling impact on back-gate biasing for FD SOI MOSFETs. / Chang, Ming Yu; Wang, Li Jing; Chiang, Meng-Hsueh.
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018. Institute of Electrical and Electronics Engineers Inc., 2019. 8640185 (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Insights to the scaling impact on back-gate biasing for FD SOI MOSFETs
AU - Chang, Ming Yu
AU - Wang, Li Jing
AU - Chiang, Meng-Hsueh
PY - 2019/2/11
Y1 - 2019/2/11
N2 - This work investigates the scaling impact on the feasibility of back-gate biasing for ultra-thin-body and BOX fully depleted SOI MOSFETs (UTBB FD SOI) at 5nm technology node. Though the effectiveness of the threshold voltage (Vt) modulation by back bias is limited due to bulk inversion as a result of silicon film scaling, such an issue of reduced Vt window can be relieved by decreasing BOX thickness as the back-gate coupling could be enhanced by thin-BOX-reduced inversion charge centroid in scaled SOI film.
AB - This work investigates the scaling impact on the feasibility of back-gate biasing for ultra-thin-body and BOX fully depleted SOI MOSFETs (UTBB FD SOI) at 5nm technology node. Though the effectiveness of the threshold voltage (Vt) modulation by back bias is limited due to bulk inversion as a result of silicon film scaling, such an issue of reduced Vt window can be relieved by decreasing BOX thickness as the back-gate coupling could be enhanced by thin-BOX-reduced inversion charge centroid in scaled SOI film.
UR - http://www.scopus.com/inward/record.url?scp=85063164860&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85063164860&partnerID=8YFLogxK
U2 - 10.1109/S3S.2018.8640185
DO - 10.1109/S3S.2018.8640185
M3 - Conference contribution
T3 - 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
BT - 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
PB - Institute of Electrical and Electronics Engineers Inc.
ER -