Insights to the scaling impact on back-gate biasing for FD SOI MOSFETs

Ming Yu Chang; Li Jing Wang; Meng-Hsueh Chiang

doi:10.1109/S3S.2018.8640185

Insights to the scaling impact on back-gate biasing for FD SOI MOSFETs

Ming Yu Chang, Li Jing Wang, Meng-Hsueh Chiang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

This work investigates the scaling impact on the feasibility of back-gate biasing for ultra-thin-body and BOX fully depleted SOI MOSFETs (UTBB FD SOI) at 5nm technology node. Though the effectiveness of the threshold voltage (V_t) modulation by back bias is limited due to bulk inversion as a result of silicon film scaling, such an issue of reduced V_t window can be relieved by decreasing BOX thickness as the back-gate coupling could be enhanced by thin-BOX-reduced inversion charge centroid in scaled SOI film.

Original language	English
Title of host publication	2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538676264
DOIs	https://doi.org/10.1109/S3S.2018.8640185
Publication status	Published - 2019 Feb 11
Event	2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 - Burlingame, United States Duration: 2018 Oct 15 → 2018 Oct 18

Publication series

Name	2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018

Conference

Conference	2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
Country/Territory	United States
City	Burlingame
Period	18-10-15 → 18-10-18

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality
Electronic, Optical and Magnetic Materials
Instrumentation

Access to Document

10.1109/S3S.2018.8640185

Cite this

Chang, M. Y., Wang, L. J., & Chiang, M-H. (2019). Insights to the scaling impact on back-gate biasing for FD SOI MOSFETs. In 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 [8640185] (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/S3S.2018.8640185

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title = "Insights to the scaling impact on back-gate biasing for FD SOI MOSFETs",

abstract = "This work investigates the scaling impact on the feasibility of back-gate biasing for ultra-thin-body and BOX fully depleted SOI MOSFETs (UTBB FD SOI) at 5nm technology node. Though the effectiveness of the threshold voltage (Vt) modulation by back bias is limited due to bulk inversion as a result of silicon film scaling, such an issue of reduced Vt window can be relieved by decreasing BOX thickness as the back-gate coupling could be enhanced by thin-BOX-reduced inversion charge centroid in scaled SOI film.",

author = "Chang, {Ming Yu} and Wang, {Li Jing} and Meng-Hsueh Chiang",

year = "2019",

month = feb,

day = "11",

doi = "10.1109/S3S.2018.8640185",

language = "English",

series = "2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018",

address = "United States",

note = "2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 ; Conference date: 15-10-2018 Through 18-10-2018",

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Chang, MY, Wang, LJ & Chiang, M-H 2019, Insights to the scaling impact on back-gate biasing for FD SOI MOSFETs. in 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018., 8640185, 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018, Institute of Electrical and Electronics Engineers Inc., 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018, Burlingame, United States, 18-10-15. https://doi.org/10.1109/S3S.2018.8640185

Insights to the scaling impact on back-gate biasing for FD SOI MOSFETs. / Chang, Ming Yu; Wang, Li Jing; Chiang, Meng-Hsueh.

2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018. Institute of Electrical and Electronics Engineers Inc., 2019. 8640185 (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - This work investigates the scaling impact on the feasibility of back-gate biasing for ultra-thin-body and BOX fully depleted SOI MOSFETs (UTBB FD SOI) at 5nm technology node. Though the effectiveness of the threshold voltage (Vt) modulation by back bias is limited due to bulk inversion as a result of silicon film scaling, such an issue of reduced Vt window can be relieved by decreasing BOX thickness as the back-gate coupling could be enhanced by thin-BOX-reduced inversion charge centroid in scaled SOI film.

AB - This work investigates the scaling impact on the feasibility of back-gate biasing for ultra-thin-body and BOX fully depleted SOI MOSFETs (UTBB FD SOI) at 5nm technology node. Though the effectiveness of the threshold voltage (Vt) modulation by back bias is limited due to bulk inversion as a result of silicon film scaling, such an issue of reduced Vt window can be relieved by decreasing BOX thickness as the back-gate coupling could be enhanced by thin-BOX-reduced inversion charge centroid in scaled SOI film.

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BT - 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018

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Chang MY, Wang LJ, Chiang M-H. Insights to the scaling impact on back-gate biasing for FD SOI MOSFETs. In 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018. Institute of Electrical and Electronics Engineers Inc. 2019. 8640185. (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018). https://doi.org/10.1109/S3S.2018.8640185

Insights to the scaling impact on back-gate biasing for FD SOI MOSFETs

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