Insights to the scaling impact on back-gate biasing for FD SOI MOSFETs

Ming Yu Chang, Li Jing Wang, Meng-Hsueh Chiang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This work investigates the scaling impact on the feasibility of back-gate biasing for ultra-thin-body and BOX fully depleted SOI MOSFETs (UTBB FD SOI) at 5nm technology node. Though the effectiveness of the threshold voltage (Vt) modulation by back bias is limited due to bulk inversion as a result of silicon film scaling, such an issue of reduced Vt window can be relieved by decreasing BOX thickness as the back-gate coupling could be enhanced by thin-BOX-reduced inversion charge centroid in scaled SOI film.

Original languageEnglish
Title of host publication2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538676264
DOIs
Publication statusPublished - 2019 Feb 11
Event2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 - Burlingame, United States
Duration: 2018 Oct 152018 Oct 18

Publication series

Name2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018

Conference

Conference2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
CountryUnited States
CityBurlingame
Period18-10-1518-10-18

Fingerprint

SOI (semiconductors)
field effect transistors
thin bodies
inversions
scaling
Silicon
silicon films
Threshold voltage
threshold voltage
centroids
Modulation
modulation
Electric potential
electric potential

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Electronic, Optical and Magnetic Materials
  • Instrumentation

Cite this

Chang, M. Y., Wang, L. J., & Chiang, M-H. (2019). Insights to the scaling impact on back-gate biasing for FD SOI MOSFETs. In 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 [8640185] (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/S3S.2018.8640185
Chang, Ming Yu ; Wang, Li Jing ; Chiang, Meng-Hsueh. / Insights to the scaling impact on back-gate biasing for FD SOI MOSFETs. 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018. Institute of Electrical and Electronics Engineers Inc., 2019. (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018).
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abstract = "This work investigates the scaling impact on the feasibility of back-gate biasing for ultra-thin-body and BOX fully depleted SOI MOSFETs (UTBB FD SOI) at 5nm technology node. Though the effectiveness of the threshold voltage (Vt) modulation by back bias is limited due to bulk inversion as a result of silicon film scaling, such an issue of reduced Vt window can be relieved by decreasing BOX thickness as the back-gate coupling could be enhanced by thin-BOX-reduced inversion charge centroid in scaled SOI film.",
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Chang, MY, Wang, LJ & Chiang, M-H 2019, Insights to the scaling impact on back-gate biasing for FD SOI MOSFETs. in 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018., 8640185, 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018, Institute of Electrical and Electronics Engineers Inc., 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018, Burlingame, United States, 18-10-15. https://doi.org/10.1109/S3S.2018.8640185

Insights to the scaling impact on back-gate biasing for FD SOI MOSFETs. / Chang, Ming Yu; Wang, Li Jing; Chiang, Meng-Hsueh.

2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018. Institute of Electrical and Electronics Engineers Inc., 2019. 8640185 (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Chang MY, Wang LJ, Chiang M-H. Insights to the scaling impact on back-gate biasing for FD SOI MOSFETs. In 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018. Institute of Electrical and Electronics Engineers Inc. 2019. 8640185. (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018). https://doi.org/10.1109/S3S.2018.8640185