Insights to the scaling impact on back-gate biasing for FD SOI MOSFETs

Ming Yu Chang, Li Jing Wang, Meng-Hsueh Chiang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

This work investigates the scaling impact on the feasibility of back-gate biasing for ultra-thin-body and BOX fully depleted SOI MOSFETs (UTBB FD SOI) at 5nm technology node. Though the effectiveness of the threshold voltage (Vt) modulation by back bias is limited due to bulk inversion as a result of silicon film scaling, such an issue of reduced Vt window can be relieved by decreasing BOX thickness as the back-gate coupling could be enhanced by thin-BOX-reduced inversion charge centroid in scaled SOI film.

Original languageEnglish
Title of host publication2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538676264
DOIs
Publication statusPublished - 2019 Feb 11
Event2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 - Burlingame, United States
Duration: 2018 Oct 152018 Oct 18

Publication series

Name2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018

Conference

Conference2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
CountryUnited States
CityBurlingame
Period18-10-1518-10-18

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Electronic, Optical and Magnetic Materials
  • Instrumentation

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