Integrated switchable inductors with symmetric differential layout

Jia Lun Wang; Yan Ru Tzeng; Tzuen Hsi Huang

doi:10.1109/APMC.2006.4429661

Integrated switchable inductors with symmetric differential layout

Jia Lun Wang, Yan Ru Tzeng, Tzuen Hsi Huang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

An integrated switchable inductor with symmetric differential layout is proposed. It can be achieved over 50% area shrinkage as compared with the traditional ones. Three testkeys with a typical switch-ON inductance of about 2.1 nH (at 1.8 GHz) were pre-designed using an electromagnetic simulator and successfully verified by tsmc's 0.18 μm RF CMOS technology. The measured ON/OFF inductance values are of 2.1 nH / 2.7 nH, 2.1 nH / 2.4 nH and 2.0 nH / 2.2 nH; and the Q-factors are of 4.1 / 6.2, 4.6 / 6.1 and 5.1 / 6.1, respectively. The Q-factor degradation of proposed switchable inductors due to the different inner turn size effect is discussed and a simple inductor lumped-circuit model is proposed with a relatively reasonable accuracy up to 10 GHz. A VCO testkey with the integration of such switchable inductor is also demonstrated.

Original language	English
Title of host publication	2006 Asia-Pacific Microwave Conference Proceedings, APMC
Pages	1369-1372
Number of pages	4
DOIs	https://doi.org/10.1109/APMC.2006.4429661
Publication status	Published - 2006 Dec 1
Event	2006 Asia-Pacific Microwave Conference, APMC - Yokohama, Japan Duration: 2006 Dec 12 → 2006 Dec 15

Publication series

Name	Asia-Pacific Microwave Conference Proceedings, APMC
Volume	2

Other

Other	2006 Asia-Pacific Microwave Conference, APMC
Country/Territory	Japan
City	Yokohama
Period	06-12-12 → 06-12-15

All Science Journal Classification (ASJC) codes

Engineering(all)

Access to Document

10.1109/APMC.2006.4429661

Cite this

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title = "Integrated switchable inductors with symmetric differential layout",

abstract = "An integrated switchable inductor with symmetric differential layout is proposed. It can be achieved over 50% area shrinkage as compared with the traditional ones. Three testkeys with a typical switch-ON inductance of about 2.1 nH (at 1.8 GHz) were pre-designed using an electromagnetic simulator and successfully verified by tsmc's 0.18 μm RF CMOS technology. The measured ON/OFF inductance values are of 2.1 nH / 2.7 nH, 2.1 nH / 2.4 nH and 2.0 nH / 2.2 nH; and the Q-factors are of 4.1 / 6.2, 4.6 / 6.1 and 5.1 / 6.1, respectively. The Q-factor degradation of proposed switchable inductors due to the different inner turn size effect is discussed and a simple inductor lumped-circuit model is proposed with a relatively reasonable accuracy up to 10 GHz. A VCO testkey with the integration of such switchable inductor is also demonstrated.",

author = "Wang, {Jia Lun} and Tzeng, {Yan Ru} and Huang, {Tzuen Hsi}",

year = "2006",

month = dec,

day = "1",

doi = "10.1109/APMC.2006.4429661",

language = "English",

isbn = "4902339099",

series = "Asia-Pacific Microwave Conference Proceedings, APMC",

pages = "1369--1372",

booktitle = "2006 Asia-Pacific Microwave Conference Proceedings, APMC",

note = "2006 Asia-Pacific Microwave Conference, APMC ; Conference date: 12-12-2006 Through 15-12-2006",

}

TY - GEN

T1 - Integrated switchable inductors with symmetric differential layout

AU - Wang, Jia Lun

AU - Tzeng, Yan Ru

AU - Huang, Tzuen Hsi

PY - 2006/12/1

Y1 - 2006/12/1

N2 - An integrated switchable inductor with symmetric differential layout is proposed. It can be achieved over 50% area shrinkage as compared with the traditional ones. Three testkeys with a typical switch-ON inductance of about 2.1 nH (at 1.8 GHz) were pre-designed using an electromagnetic simulator and successfully verified by tsmc's 0.18 μm RF CMOS technology. The measured ON/OFF inductance values are of 2.1 nH / 2.7 nH, 2.1 nH / 2.4 nH and 2.0 nH / 2.2 nH; and the Q-factors are of 4.1 / 6.2, 4.6 / 6.1 and 5.1 / 6.1, respectively. The Q-factor degradation of proposed switchable inductors due to the different inner turn size effect is discussed and a simple inductor lumped-circuit model is proposed with a relatively reasonable accuracy up to 10 GHz. A VCO testkey with the integration of such switchable inductor is also demonstrated.

AB - An integrated switchable inductor with symmetric differential layout is proposed. It can be achieved over 50% area shrinkage as compared with the traditional ones. Three testkeys with a typical switch-ON inductance of about 2.1 nH (at 1.8 GHz) were pre-designed using an electromagnetic simulator and successfully verified by tsmc's 0.18 μm RF CMOS technology. The measured ON/OFF inductance values are of 2.1 nH / 2.7 nH, 2.1 nH / 2.4 nH and 2.0 nH / 2.2 nH; and the Q-factors are of 4.1 / 6.2, 4.6 / 6.1 and 5.1 / 6.1, respectively. The Q-factor degradation of proposed switchable inductors due to the different inner turn size effect is discussed and a simple inductor lumped-circuit model is proposed with a relatively reasonable accuracy up to 10 GHz. A VCO testkey with the integration of such switchable inductor is also demonstrated.

UR - http://www.scopus.com/inward/record.url?scp=44949205439&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=44949205439&partnerID=8YFLogxK

U2 - 10.1109/APMC.2006.4429661

DO - 10.1109/APMC.2006.4429661

M3 - Conference contribution

AN - SCOPUS:44949205439

SN - 4902339099

SN - 9784902339093

T3 - Asia-Pacific Microwave Conference Proceedings, APMC

SP - 1369

EP - 1372

BT - 2006 Asia-Pacific Microwave Conference Proceedings, APMC

T2 - 2006 Asia-Pacific Microwave Conference, APMC

Y2 - 12 December 2006 through 15 December 2006

ER -

Integrated switchable inductors with symmetric differential layout

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