In this article, the direct-coupled FET logic (DCFL) inverters are implemented by co-integrated AlGaAs/InGaAs depletion-mode and enhancement-mode pseudomorphic high electron mobility transistors with virtual channel layers, and the inverters with varying gate width of the depletion-mode transistors are demonstrated. The experimental results show that the drain current IDS (mA/mm) and gm (mS/mm) per unit gate width increases as the gate widths of the depletion-mode devices decrease. This is attributed to the fact that the drain current and transconductance values are related to the channel-to-source resistance and the source contact resistance. When the gate width is reduced, the source pad contact area is only slightly changed and the IDS (mA/mm) as well as the transconductance gm (mS/mm) will increase. In addition, it is also observed that for the reduce of the gate width of the depletion-mode devices, the transfer characteristics of the DCFL inverters are steep and shift to the left due to the smaller drain saturation current of the load transistor.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials