Investigation of step-doped channel heterostructure field-effect transistor

Wen Chau Liu, Lih Wen Laih, Jung Hui Tsai, Jing Yuh Chen, Wei Chou Wang, Po Hung Lin

Research output: Contribution to conferencePaperpeer-review

3 Citations (Scopus)

Abstract

Two kinds of heterostructure field-effect transistor (FET) with an InGaAs step-doped-channel (SDC) profile have been fabricated and demonstrated. For the 1×100 μm2 gated dimension, the maximum drain saturation currents were 735 and 675 mA/mm, the maximum transconductances 200 and 232 mS/mm, the gate breakdown voltages 15 V and 12 V, the wide gate voltage swing 3.3 and 2.6 V with transconductance gm higher than 150 mS/mm. A simple model is employed to analyze the performance of threshold voltage VT and the threshold voltage -3.7 and -1.8 V are obtained, respectively. These good performances show the studied SDCFET have good potential for high-speed, high-power circuit applications.

Original languageEnglish
Pages251-254
Number of pages4
Publication statusPublished - 1996 Dec 1
EventProceedings of the 1996 Conference on Optoelectronic & Microelectronic Materials and Devices, COMMAD - Canberra, Aust
Duration: 1996 Dec 81996 Dec 11

Other

OtherProceedings of the 1996 Conference on Optoelectronic & Microelectronic Materials and Devices, COMMAD
CityCanberra, Aust
Period96-12-0896-12-11

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Fingerprint Dive into the research topics of 'Investigation of step-doped channel heterostructure field-effect transistor'. Together they form a unique fingerprint.

Cite this