Investigation of Various Bumps and Redistribution Lines to Inhibit Protected Silicon Nitride Cracks in High Pattern Density Chip Package

Mechanical stress related to chip packaging failure is the most common reliability issue in semiconductor devices, especially for high pattern density of very-large-scale integration. In this paper, redistribution lines (RDL) corresponding to gold and copper materials with capped layers (Sn-Ag and Au-Ni) were evaluated to investigate the structure dependency on the mechanical properties of intermetallic compounds, and to provide a solution to improve chip package reliability in regard to protect Si₃N₄ cracks. The simulation results revealed that a thicker Si₃N₄ film combined with the corner rounding of bump/RDL structures could mitigate Si₃N₄ film cracks. Voids induced by the fine pitch configuration of the top Al increase the potential risk of Si₃N₄ cracks during chip packaging. The reflow temperature is a major factor increasing the thermal stress in RDL patterns rather than from the bump structure. A high temperature storage test applied to the Cu pillar/Sn-Ag capping was used to investigate the intermetallic compound growth, shear strength, and hardness.