IDDQ fault model to facilitate the design of built-in current sensor (BICSs)

Jing Jou Tang, Bin Da Liu, Kuen Jong Lee

Research output: Contribution to journalConference articlepeer-review

Abstract

In this paper, we present an efficient and accurate IDDQ fault modeling technique for digital CMOS circuit. Both the normal and faulty 'current' behaviors of a CMOS digital circuit can be described by this model. Also the parasitic capacitive and inductive parameters can be emulated. A formal method for creating this model from any given CMOS circuit is outlined. Using this model, circuit design of built-in current sensors (BICSs) can be designed and validated without introducing the actual circuit under test (CUT) which implanted a fault. Experimental data for the application to the design of BICSs is also given.

Original languageEnglish
Pages (from-to)393-396
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume1
Publication statusPublished - 1995 Jan 1
EventProceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA
Duration: 1995 Apr 301995 May 3

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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