IDDQ fault model to facilitate the design of built-in current sensor (BICSs)

Jing Jou Tang; Bin Da Liu; Kuen Jong Lee

I_DDQ fault model to facilitate the design of built-in current sensor (BICSs)

Jing Jou Tang
, Bin Da Liu
, Kuen Jong Lee

Department of Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

Abstract

In this paper, we present an efficient and accurate I_DDQ fault modeling technique for digital CMOS circuit. Both the normal and faulty 'current' behaviors of a CMOS digital circuit can be described by this model. Also the parasitic capacitive and inductive parameters can be emulated. A formal method for creating this model from any given CMOS circuit is outlined. Using this model, circuit design of built-in current sensors (BICSs) can be designed and validated without introducing the actual circuit under test (CUT) which implanted a fault. Experimental data for the application to the design of BICSs is also given.

Original language	English
Pages (from-to)	393-396
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	1
Publication status	Published - 1995 Jan 1
Event	Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA Duration: 1995 Apr 30 → 1995 May 3

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Cite this

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title = "IDDQ fault model to facilitate the design of built-in current sensor (BICSs)",

abstract = "In this paper, we present an efficient and accurate IDDQ fault modeling technique for digital CMOS circuit. Both the normal and faulty 'current' behaviors of a CMOS digital circuit can be described by this model. Also the parasitic capacitive and inductive parameters can be emulated. A formal method for creating this model from any given CMOS circuit is outlined. Using this model, circuit design of built-in current sensors (BICSs) can be designed and validated without introducing the actual circuit under test (CUT) which implanted a fault. Experimental data for the application to the design of BICSs is also given.",

author = "Tang, \{Jing Jou\} and Liu, \{Bin Da\} and Lee, \{Kuen Jong\}",

year = "1995",

month = jan,

day = "1",

language = "English",

volume = "1",

pages = "393--396",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) ; Conference date: 30-04-1995 Through 03-05-1995",

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TY - JOUR

T1 - IDDQ fault model to facilitate the design of built-in current sensor (BICSs)

AU - Tang, Jing Jou

AU - Liu, Bin Da

AU - Lee, Kuen Jong

PY - 1995/1/1

Y1 - 1995/1/1

N2 - In this paper, we present an efficient and accurate IDDQ fault modeling technique for digital CMOS circuit. Both the normal and faulty 'current' behaviors of a CMOS digital circuit can be described by this model. Also the parasitic capacitive and inductive parameters can be emulated. A formal method for creating this model from any given CMOS circuit is outlined. Using this model, circuit design of built-in current sensors (BICSs) can be designed and validated without introducing the actual circuit under test (CUT) which implanted a fault. Experimental data for the application to the design of BICSs is also given.

AB - In this paper, we present an efficient and accurate IDDQ fault modeling technique for digital CMOS circuit. Both the normal and faulty 'current' behaviors of a CMOS digital circuit can be described by this model. Also the parasitic capacitive and inductive parameters can be emulated. A formal method for creating this model from any given CMOS circuit is outlined. Using this model, circuit design of built-in current sensors (BICSs) can be designed and validated without introducing the actual circuit under test (CUT) which implanted a fault. Experimental data for the application to the design of BICSs is also given.

UR - https://www.scopus.com/pages/publications/0029194179

UR - https://www.scopus.com/pages/publications/0029194179#tab=citedBy

M3 - Conference article

AN - SCOPUS:0029194179

SN - 0271-4310

VL - 1

SP - 393

EP - 396

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3)

Y2 - 30 April 1995 through 3 May 1995

ER -

I_DDQ fault model to facilitate the design of built-in current sensor (BICSs)

Abstract

All Science Journal Classification (ASJC) codes

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