Kernel Aware Warp Scheduler

Sen Chih Tsai, Yu Xiang Su, Yu Han Chin, Wei Zhong Ceng, Chung Ho Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Observing that thread blocks of different kernels that use different functional units should be sent to the same SM (Streaming Multiprocessor) to promote the utilization of functional units, we propose a kernel-aware warp scheduler for GPGPUs. The proposed Kernel Aware Warp Scheduler uses the profiling information of the executed kernels to issue instructions from the right warp. The experimental results based on our HSAIL simulation platform show that the overall performance of the kernel execution improves by about 20% on average. The speedup comes from the increased utilization of functional units and effectiveness in hiding of the memory latency due to the proposed warp scheduling policy.

Original languageEnglish
Title of host publication2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538648810
DOIs
Publication statusPublished - 2018 Apr 26
Event2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, Italy
Duration: 2018 May 272018 May 30

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2018-May
ISSN (Print)0271-4310

Other

Other2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
CountryItaly
CityFlorence
Period18-05-2718-05-30

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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