Layout compaction with minimized delay bound on timing critical paths

Lih Yang Wang, Yen Tai Lai, Bin Da Liu, Tin Chung Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

A layout compaction problem which aims at both the performance improvement and area reduction is studied. A new algorithm which first determines the minimal delay bound for performance critical paths and then minimizes the layout size without affecting the previous consideration is proposed. These two steps are formulated as two linear programs and solved by the simplex algorithm. Effective graph-based techniques for finding the initial solution and reducing the problem dimension are employed to reduce the execution time.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherPubl by IEEE
Pages1849-1852
Number of pages4
ISBN (Print)0780312813
Publication statusPublished - 1993 Jan 1
EventProceedings of the 1993 IEEE International Symposium on Circuits and Systems - Chicago, IL, USA
Duration: 1993 May 31993 May 6

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume3
ISSN (Print)0271-4310

Other

OtherProceedings of the 1993 IEEE International Symposium on Circuits and Systems
CityChicago, IL, USA
Period93-05-0393-05-06

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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  • Cite this

    Wang, L. Y., Lai, Y. T., Liu, B. D., & Chang, T. C. (1993). Layout compaction with minimized delay bound on timing critical paths. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 1849-1852). (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 3). Publ by IEEE.