Layout compaction with minimized delay bound on timing critical paths

Lih Yang Wang; Yen Tai Lai; Bin Da Liu; Tin Chung Chang

Layout compaction with minimized delay bound on timing critical paths

Lih Yang Wang, Yen Tai Lai, Bin Da Liu, Tin Chung Chang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

A layout compaction problem which aims at both the performance improvement and area reduction is studied. A new algorithm which first determines the minimal delay bound for performance critical paths and then minimizes the layout size without affecting the previous consideration is proposed. These two steps are formulated as two linear programs and solved by the simplex algorithm. Effective graph-based techniques for finding the initial solution and reducing the problem dimension are employed to reduce the execution time.

Original language	English
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems
Publisher	Publ by IEEE
Pages	1849-1852
Number of pages	4
ISBN (Print)	0780312813
Publication status	Published - 1993
Event	Proceedings of the 1993 IEEE International Symposium on Circuits and Systems - Chicago, IL, USA Duration: 1993 May 3 → 1993 May 6

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	3
ISSN (Print)	0271-4310

Other

Other	Proceedings of the 1993 IEEE International Symposium on Circuits and Systems
City	Chicago, IL, USA
Period	93-05-03 → 93-05-06

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Cite this

@inproceedings{2616093b16624e6db77d73c368a7b0a6,

title = "Layout compaction with minimized delay bound on timing critical paths",

abstract = "A layout compaction problem which aims at both the performance improvement and area reduction is studied. A new algorithm which first determines the minimal delay bound for performance critical paths and then minimizes the layout size without affecting the previous consideration is proposed. These two steps are formulated as two linear programs and solved by the simplex algorithm. Effective graph-based techniques for finding the initial solution and reducing the problem dimension are employed to reduce the execution time.",

author = "Wang, {Lih Yang} and Lai, {Yen Tai} and Liu, {Bin Da} and Chang, {Tin Chung}",

year = "1993",

language = "English",

isbn = "0780312813",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Publ by IEEE",

pages = "1849--1852",

booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",

note = "Proceedings of the 1993 IEEE International Symposium on Circuits and Systems ; Conference date: 03-05-1993 Through 06-05-1993",

}

Wang, LY, Lai, YT, Liu, BD & Chang, TC 1993, Layout compaction with minimized delay bound on timing critical paths. in Proceedings - IEEE International Symposium on Circuits and Systems. Proceedings - IEEE International Symposium on Circuits and Systems, vol. 3, Publ by IEEE, pp. 1849-1852, Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, Chicago, IL, USA, 93-05-03.

Layout compaction with minimized delay bound on timing critical paths. / Wang, Lih Yang; Lai, Yen Tai; Liu, Bin Da; Chang, Tin Chung.

Proceedings - IEEE International Symposium on Circuits and Systems. Publ by IEEE, 1993. p. 1849-1852 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 3).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Layout compaction with minimized delay bound on timing critical paths

AU - Wang, Lih Yang

AU - Lai, Yen Tai

AU - Liu, Bin Da

AU - Chang, Tin Chung

PY - 1993

Y1 - 1993

N2 - A layout compaction problem which aims at both the performance improvement and area reduction is studied. A new algorithm which first determines the minimal delay bound for performance critical paths and then minimizes the layout size without affecting the previous consideration is proposed. These two steps are formulated as two linear programs and solved by the simplex algorithm. Effective graph-based techniques for finding the initial solution and reducing the problem dimension are employed to reduce the execution time.

AB - A layout compaction problem which aims at both the performance improvement and area reduction is studied. A new algorithm which first determines the minimal delay bound for performance critical paths and then minimizes the layout size without affecting the previous consideration is proposed. These two steps are formulated as two linear programs and solved by the simplex algorithm. Effective graph-based techniques for finding the initial solution and reducing the problem dimension are employed to reduce the execution time.

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UR - http://www.scopus.com/inward/citedby.url?scp=0027313781&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0027313781

SN - 0780312813

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 1849

EP - 1852

BT - Proceedings - IEEE International Symposium on Circuits and Systems

PB - Publ by IEEE

T2 - Proceedings of the 1993 IEEE International Symposium on Circuits and Systems

Y2 - 3 May 1993 through 6 May 1993

ER -

Layout compaction with minimized delay bound on timing critical paths

Abstract

Publication series

Other

All Science Journal Classification (ASJC) codes

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