Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test

Hsuan Wei Liu, Bing Yang Lin, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

The cell-aware test (CAT) methodology was previously proposed to target cell-internal faults that cannot be easily detected by gate-level stuck-at fault (SAF) patterns generated by conventional ATPG. It was shown to reduce the defect level on CMOS-based designs, with the help of detailed defect injected transistor-level circuit simulation and defect-enhanced SAF ATPG. The detailed transistor-level circuit simulation has been considered an issue in CAT, as it is very time consuming. The problem mainly lies in that all parasitic capacitors and resistors extracted from cell layout are considered as defect targets, so the defect set is large. To reduce the defect set, and therefore the circuit simulation time, we take layout into consideration when we construct the defect set for each cell, effectively removing the redundant or unnecessary defects and therefore reducing the circuit simulation time dramatically. We propose a generalized approach that can be used to build the fault models based on the cell layout, where the generated faults are closer to the realistic physical defects on the layout, so the number of faults is significantly reduced. The proposed method is verified by commercial 180nm and 350nm CMOS standard cell library, and the circuit simulation time is reduced to only 19% or even lower as compared with the original CAT methodology.

Original languageEnglish
Title of host publicationProceedings - 2016 IEEE 25th Asian Test Symposium, ATS 2016
PublisherIEEE Computer Society
Pages156-160
Number of pages5
ISBN (Electronic)9781509038084
DOIs
Publication statusPublished - 2016 Dec 22
Event25th IEEE Asian Test Symposium, ATS 2016 - Hiroshima, Japan
Duration: 2016 Nov 212016 Nov 24

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735

Other

Other25th IEEE Asian Test Symposium, ATS 2016
CountryJapan
CityHiroshima
Period16-11-2116-11-24

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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  • Cite this

    Liu, H. W., Lin, B. Y., & Wu, C. W. (2016). Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test. In Proceedings - 2016 IEEE 25th Asian Test Symposium, ATS 2016 (pp. 156-160). [7796105] (Proceedings of the Asian Test Symposium). IEEE Computer Society. https://doi.org/10.1109/ATS.2016.25