Leakage and aging optimization using transmission gate-based technique

Ing Chao Lin, Chin Hong Lin, Kuan Hui Li

Research output: Contribution to journalArticlepeer-review

31 Citations (Scopus)


Negative bias temperature instability (NBTI), which can degrade the switching speed of PMOS transistors, has become a major reliability challenge. Reducing leakage consumption is one of the major design goals. The gate replacement (GR) technique is an effective way to reduce both the NBTI effect and leakage. This technique, however, has less flexibility because the replaced gate can only produce one output value and careful algorithms are needed to decide the output value of the replaced gate. In this paper, we propose a novel transmission gate-based technique to minimize NBTI-induced degradation and leakage. This technique, which can offer logic 1 for NBTI mitigation and logic 0 for leakage reduction, provides higher flexibility, as compared to the GR technique. Simulation results show that our proposed technique has up to 20× and 2.16×, on average, improvement on NBTI-induced degradation with comparable leakage power reduction. With a 19.19% area penalty, combining our technique and the GR can reduce 17.92% of the total leakage power and 32.36% of NBTI-induced circuit degradation.

Original languageEnglish
Article number6387701
Pages (from-to)87-99
Number of pages13
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number1
Publication statusPublished - 2013 Jan 10

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


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