Leakage control with efficient use of transistor stacks in single threshold CMOS

Mark C. Johnson, Dinesh Somasekhar, Lih Yih Chiou, Kaushik Roy

Research output: Contribution to journalArticlepeer-review

138 Citations (Scopus)


The state dependence of leakage can be exploited to obtain modest leakage savings in complementary metal-oxide-semiconductor (CMOS) circuits, However, one can modify circuits considering state dependence and achieve larger savings. We identify a low-leakage state and insert leakage-control transistors only where needed. Leakage levels are on the order of 35% to 90% lower than those obtained by state dependence alone. Using a modified standard-cell-design flow, area overhead for combinational logic was found to be on the order of 18%. The proposed technique minimizes performance impact, does not require multiple-threshold voltages, and supports a standard-cell-design flow.

Original languageEnglish
Pages (from-to)1-5
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number1
Publication statusPublished - 2002 Feb

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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