Leakage control with efficient use of transistor stacks in single threshold CMOS

Mark C. Johnson; Dinesh Somasekhar; Lih Yih Chiou; Kaushik Roy

doi:10.1109/92.988724

Leakage control with efficient use of transistor stacks in single threshold CMOS

Mark C. Johnson, Dinesh Somasekhar, Lih Yih Chiou, Kaushik Roy

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

128 Citations (Scopus)

Abstract

The state dependence of leakage can be exploited to obtain modest leakage savings in complementary metal-oxide-semiconductor (CMOS) circuits, However, one can modify circuits considering state dependence and achieve larger savings. We identify a low-leakage state and insert leakage-control transistors only where needed. Leakage levels are on the order of 35% to 90% lower than those obtained by state dependence alone. Using a modified standard-cell-design flow, area overhead for combinational logic was found to be on the order of 18%. The proposed technique minimizes performance impact, does not require multiple-threshold voltages, and supports a standard-cell-design flow.

Original language	English
Pages (from-to)	1-5
Number of pages	5
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	10
Issue number	1
DOIs	https://doi.org/10.1109/92.988724
Publication status	Published - 2002 Feb

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/92.988724

Cite this

@article{8dcc497639874ed5bf59a0209e0d4465,

title = "Leakage control with efficient use of transistor stacks in single threshold CMOS",

abstract = "The state dependence of leakage can be exploited to obtain modest leakage savings in complementary metal-oxide-semiconductor (CMOS) circuits, However, one can modify circuits considering state dependence and achieve larger savings. We identify a low-leakage state and insert leakage-control transistors only where needed. Leakage levels are on the order of 35% to 90% lower than those obtained by state dependence alone. Using a modified standard-cell-design flow, area overhead for combinational logic was found to be on the order of 18%. The proposed technique minimizes performance impact, does not require multiple-threshold voltages, and supports a standard-cell-design flow.",

author = "Johnson, {Mark C.} and Dinesh Somasekhar and Chiou, {Lih Yih} and Kaushik Roy",

note = "Funding Information: Manuscript received May 1, 2001. This work was supported in part by ARPA (F33615-95-C-1625), by NSF CAREER Award (9501869-MIP), ASSERT Program (DAAH04-96-1-0222), SRC, and in part by Intel Corporation. A prior version of this work was presented at the 36th Design Automation Conference.",

year = "2002",

month = feb,

doi = "10.1109/92.988724",

language = "English",

volume = "10",

pages = "1--5",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "1",

}

TY - JOUR

T1 - Leakage control with efficient use of transistor stacks in single threshold CMOS

AU - Johnson, Mark C.

AU - Somasekhar, Dinesh

AU - Chiou, Lih Yih

AU - Roy, Kaushik

N1 - Funding Information: Manuscript received May 1, 2001. This work was supported in part by ARPA (F33615-95-C-1625), by NSF CAREER Award (9501869-MIP), ASSERT Program (DAAH04-96-1-0222), SRC, and in part by Intel Corporation. A prior version of this work was presented at the 36th Design Automation Conference.

PY - 2002/2

Y1 - 2002/2

N2 - The state dependence of leakage can be exploited to obtain modest leakage savings in complementary metal-oxide-semiconductor (CMOS) circuits, However, one can modify circuits considering state dependence and achieve larger savings. We identify a low-leakage state and insert leakage-control transistors only where needed. Leakage levels are on the order of 35% to 90% lower than those obtained by state dependence alone. Using a modified standard-cell-design flow, area overhead for combinational logic was found to be on the order of 18%. The proposed technique minimizes performance impact, does not require multiple-threshold voltages, and supports a standard-cell-design flow.

AB - The state dependence of leakage can be exploited to obtain modest leakage savings in complementary metal-oxide-semiconductor (CMOS) circuits, However, one can modify circuits considering state dependence and achieve larger savings. We identify a low-leakage state and insert leakage-control transistors only where needed. Leakage levels are on the order of 35% to 90% lower than those obtained by state dependence alone. Using a modified standard-cell-design flow, area overhead for combinational logic was found to be on the order of 18%. The proposed technique minimizes performance impact, does not require multiple-threshold voltages, and supports a standard-cell-design flow.

UR - http://www.scopus.com/inward/record.url?scp=0036477154&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0036477154&partnerID=8YFLogxK

U2 - 10.1109/92.988724

DO - 10.1109/92.988724

M3 - Article

AN - SCOPUS:0036477154

VL - 10

SP - 1

EP - 5

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 1

ER -

Leakage control with efficient use of transistor stacks in single threshold CMOS

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