Leveraging nMOS Negative Differential Resistance for Low Power, High Reliability Magnetic Memory

Shaodi Wang, Andrew Pan, Cecile Grezes, Pedram Khalili Amiri, Kang L. Wang, Chi On Chui, Puneet Gupta

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)

Abstract

We propose, demonstrate, and assess a nontunneling-based nMOS voltage-controlled negative differential resistance (V-NDR) concept for overcoming the intrinsic efficiency and reliability shortcomings of magnetic random access memory memories (MRAM). Using nMOS V-NDR circuits in series with MRAM tunnel junctions, we experimentally observe 40 times reduction in current during switching, enabling write termination and read margin amplification. Large scale Monte Carlo simulations also show 5X improvement in write energy savings and demonstrate the robustness of the scheme against device variability.

Original languageEnglish
Article number8024018
Pages (from-to)4084-4090
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume64
Issue number10
DOIs
Publication statusPublished - 2017 Oct

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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