Linearity improvement of cascode CMOS LNA using a diode connected NMOS transistor with a parallel RC circuit

C. P. Chang, W. C. Chien, C. C. Su, Y. H. Wang, J. H. Chen

Research output: Contribution to journalArticlepeer-review

9 Citations (Scopus)

Abstract

A fully integrated 5.5 GHz high-linearity low noise amplifier (LNA) using post-linearization technique, implemented in a 0.18 μm RF CMOS technology, is demonstrated. The proposed technique adopts an additional folded diode with a parallel RC circuit as an intermodulation distortion (IMD) sinker. The proposed LNA not only achieves high linearity, but also minimizes the degradation of gain, noise figure (NF) and power consumption. The LNA achieves an input third-order intercept point (IIP3) of +8.33 dBm, a power gain of 10.02 dB, and a NF of 3.05 dB at 5.5 GHz biased at 6mA from a 1.8 V power supply.

Original languageEnglish
Pages (from-to)29-38
Number of pages10
JournalProgress In Electromagnetics Research C
Volume17
DOIs
Publication statusPublished - 2010

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials

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