Logic and fault simulation by cellular automata

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

We propose a massively parallel architecture to speed up the logic and fault simulation. We use a 2-D cellular automata (CA) to implement the logic and fault simulation of combinational circuits. Our CA has six cell states, and operates in a pipelined fashion. Experimental results on ISCAS85 benchmark circuits show that our CA outperforms the previously reported parallel simulators. As to pure logic simulation, our CA performs up to 9.24 billion GEPS using a 20 MHz clock and 8-bit words as opposed to 5 billion GEPS.

Original languageEnglish
Title of host publicationProceedings of the European Design and Test Conference
Editors Anon
PublisherPubl by IEEE
Pages552-556
Number of pages5
ISBN (Print)0818654112
Publication statusPublished - 1994 Jan 1
EventProceedings of the European Design and Test Conference - Paris, Fr
Duration: 1994 Feb 281994 Mar 3

Publication series

NameProceedings of the European Design and Test Conference

Conference

ConferenceProceedings of the European Design and Test Conference
CityParis, Fr
Period94-02-2894-03-03

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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