Logic design using the PLAs with limited I/O pins and product terms

Yau-Hwang Kuo, Ruey Rong Wang, Ling Yeung Kung

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

When commercial programmable logic arrays (PLA) are used in logic design, the limitation on the number of I/O pins and product terms is an important issue. For overcoming this problem, a logic decomposition method, which can decompose a complex Boolean function into several subfunctions adaptable to be realized in some commercially available PLAs, is proposed in this paper. Then a two-level AND-OR gate network is used to connect the PLAs for realizing the original Boolean function. In fact, this AND-OR gate network can also be implemented with a PLA chip. Therefore, this method, which realizes a large Boolean function with a multiple-level PLA network, provides a practical solution to the problem of logic design with PLA chips. This paper also describes a quick algorithm for minimizing the Boolean function to be realized by PLAs.

Original languageEnglish
Pages (from-to)27-31
Number of pages5
JournalMicroprocessing and Microprogramming
Volume23
Issue number1-5
DOIs
Publication statusPublished - 1988 Jan 1

Fingerprint

Logic design
Boolean functions
Decomposition

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Kuo, Yau-Hwang ; Wang, Ruey Rong ; Kung, Ling Yeung. / Logic design using the PLAs with limited I/O pins and product terms. In: Microprocessing and Microprogramming. 1988 ; Vol. 23, No. 1-5. pp. 27-31.
@article{1d2470cc0a8d428e824c13d2855ffc2e,
title = "Logic design using the PLAs with limited I/O pins and product terms",
abstract = "When commercial programmable logic arrays (PLA) are used in logic design, the limitation on the number of I/O pins and product terms is an important issue. For overcoming this problem, a logic decomposition method, which can decompose a complex Boolean function into several subfunctions adaptable to be realized in some commercially available PLAs, is proposed in this paper. Then a two-level AND-OR gate network is used to connect the PLAs for realizing the original Boolean function. In fact, this AND-OR gate network can also be implemented with a PLA chip. Therefore, this method, which realizes a large Boolean function with a multiple-level PLA network, provides a practical solution to the problem of logic design with PLA chips. This paper also describes a quick algorithm for minimizing the Boolean function to be realized by PLAs.",
author = "Yau-Hwang Kuo and Wang, {Ruey Rong} and Kung, {Ling Yeung}",
year = "1988",
month = "1",
day = "1",
doi = "10.1016/0165-6074(88)90330-4",
language = "English",
volume = "23",
pages = "27--31",
journal = "Journal of Systems Architecture",
issn = "1383-7621",
publisher = "Elsevier",
number = "1-5",

}

Logic design using the PLAs with limited I/O pins and product terms. / Kuo, Yau-Hwang; Wang, Ruey Rong; Kung, Ling Yeung.

In: Microprocessing and Microprogramming, Vol. 23, No. 1-5, 01.01.1988, p. 27-31.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Logic design using the PLAs with limited I/O pins and product terms

AU - Kuo, Yau-Hwang

AU - Wang, Ruey Rong

AU - Kung, Ling Yeung

PY - 1988/1/1

Y1 - 1988/1/1

N2 - When commercial programmable logic arrays (PLA) are used in logic design, the limitation on the number of I/O pins and product terms is an important issue. For overcoming this problem, a logic decomposition method, which can decompose a complex Boolean function into several subfunctions adaptable to be realized in some commercially available PLAs, is proposed in this paper. Then a two-level AND-OR gate network is used to connect the PLAs for realizing the original Boolean function. In fact, this AND-OR gate network can also be implemented with a PLA chip. Therefore, this method, which realizes a large Boolean function with a multiple-level PLA network, provides a practical solution to the problem of logic design with PLA chips. This paper also describes a quick algorithm for minimizing the Boolean function to be realized by PLAs.

AB - When commercial programmable logic arrays (PLA) are used in logic design, the limitation on the number of I/O pins and product terms is an important issue. For overcoming this problem, a logic decomposition method, which can decompose a complex Boolean function into several subfunctions adaptable to be realized in some commercially available PLAs, is proposed in this paper. Then a two-level AND-OR gate network is used to connect the PLAs for realizing the original Boolean function. In fact, this AND-OR gate network can also be implemented with a PLA chip. Therefore, this method, which realizes a large Boolean function with a multiple-level PLA network, provides a practical solution to the problem of logic design with PLA chips. This paper also describes a quick algorithm for minimizing the Boolean function to be realized by PLAs.

UR - http://www.scopus.com/inward/record.url?scp=0023982918&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0023982918&partnerID=8YFLogxK

U2 - 10.1016/0165-6074(88)90330-4

DO - 10.1016/0165-6074(88)90330-4

M3 - Article

VL - 23

SP - 27

EP - 31

JO - Journal of Systems Architecture

JF - Journal of Systems Architecture

SN - 1383-7621

IS - 1-5

ER -