Logic testing of switch-level faults for CMOS unate networks

Yeong Ruey Shieh, Cheng W. Wu

Research output: Contribution to conferencePaper

Abstract

The main obstacle in testing CMOS stuck-on faults is that the test vectors must be applied relatively slowly for static current monitoring to be carried out reliably. As to stuck-open faults, they can create unintended states such that test generation is greatly complicated. In this paper, we propose a design for testability (DFT) approach to detect stuck-on and stuck-open faults using voltage (logic-level) monitoring instead of current monitoring. The area overhead and performance penalty is small.

Original languageEnglish
Pages212-215
Number of pages4
Publication statusPublished - 1997 Dec 1
Event7th International Symposium on IC Technology, Systems and Applications ISIC 97 - Singapore, Singapore
Duration: 1997 Sep 101997 Sep 12

Other

Other7th International Symposium on IC Technology, Systems and Applications ISIC 97
CountrySingapore
CitySingapore
Period97-09-1097-09-12

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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  • Cite this

    Shieh, Y. R., & Wu, C. W. (1997). Logic testing of switch-level faults for CMOS unate networks. 212-215. Paper presented at 7th International Symposium on IC Technology, Systems and Applications ISIC 97, Singapore, Singapore.