| Original language | English |
|---|---|
| Title of host publication | 7th International Symposium on IC Technology, Systems & Applications (ISIC) |
| Place of Publication | Singapore |
| Pages | 212-215 |
| Publication status | Published - 1997 Sept |
Logic testing of switch-level faults for CMOS unate networks
Y.-R. Shieh, Cheng-Wen Wu
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution