Logic testing of switch-level faults for CMOS unate networks

Y.-R. Shieh, Cheng-Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Original languageEnglish
Title of host publication7th International Symposium on IC Technology, Systems & Applications (ISIC)
Place of PublicationSingapore
Pages212-215
Publication statusPublished - 1997 Sep

Cite this

Shieh, Y-R., & Wu, C-W. (1997). Logic testing of switch-level faults for CMOS unate networks. In 7th International Symposium on IC Technology, Systems & Applications (ISIC) (pp. 212-215).