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Logic testing of switch-level faults for CMOS unate networks

  • Y.-R. Shieh
  • , Cheng-Wen Wu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Original languageEnglish
Title of host publication7th International Symposium on IC Technology, Systems & Applications (ISIC)
Place of PublicationSingapore
Pages212-215
Publication statusPublished - 1997 Sept

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