Logic testing of switch-level faults for CMOS unate networks

Yeong Ruey Shieh; Cheng W. Wu

Logic testing of switch-level faults for CMOS unate networks

Yeong Ruey Shieh
, Cheng W. Wu

Department of Electrical Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract

The main obstacle in testing CMOS stuck-on faults is that the test vectors must be applied relatively slowly for static current monitoring to be carried out reliably. As to stuck-open faults, they can create unintended states such that test generation is greatly complicated. In this paper, we propose a design for testability (DFT) approach to detect stuck-on and stuck-open faults using voltage (logic-level) monitoring instead of current monitoring. The area overhead and performance penalty is small.

Original language	English
Pages	212-215
Number of pages	4
Publication status	Published - 1997 Dec 1
Event	7th International Symposium on IC Technology, Systems and Applications ISIC 97 - Singapore, Singapore Duration: 1997 Sept 10 → 1997 Sept 12

Other

Other	7th International Symposium on IC Technology, Systems and Applications ISIC 97
Country/Territory	Singapore
City	Singapore
Period	97-09-10 → 97-09-12

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Cite this

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title = "Logic testing of switch-level faults for CMOS unate networks",

abstract = "The main obstacle in testing CMOS stuck-on faults is that the test vectors must be applied relatively slowly for static current monitoring to be carried out reliably. As to stuck-open faults, they can create unintended states such that test generation is greatly complicated. In this paper, we propose a design for testability (DFT) approach to detect stuck-on and stuck-open faults using voltage (logic-level) monitoring instead of current monitoring. The area overhead and performance penalty is small.",

author = "Shieh, \{Yeong Ruey\} and Wu, \{Cheng W.\}",

year = "1997",

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day = "1",

language = "English",

pages = "212--215",

note = "7th International Symposium on IC Technology, Systems and Applications ISIC 97 ; Conference date: 10-09-1997 Through 12-09-1997",

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TY - CONF

T1 - Logic testing of switch-level faults for CMOS unate networks

AU - Shieh, Yeong Ruey

AU - Wu, Cheng W.

PY - 1997/12/1

Y1 - 1997/12/1

N2 - The main obstacle in testing CMOS stuck-on faults is that the test vectors must be applied relatively slowly for static current monitoring to be carried out reliably. As to stuck-open faults, they can create unintended states such that test generation is greatly complicated. In this paper, we propose a design for testability (DFT) approach to detect stuck-on and stuck-open faults using voltage (logic-level) monitoring instead of current monitoring. The area overhead and performance penalty is small.

AB - The main obstacle in testing CMOS stuck-on faults is that the test vectors must be applied relatively slowly for static current monitoring to be carried out reliably. As to stuck-open faults, they can create unintended states such that test generation is greatly complicated. In this paper, we propose a design for testability (DFT) approach to detect stuck-on and stuck-open faults using voltage (logic-level) monitoring instead of current monitoring. The area overhead and performance penalty is small.

UR - https://www.scopus.com/pages/publications/1842780106

UR - https://www.scopus.com/pages/publications/1842780106#tab=citedBy

M3 - Paper

AN - SCOPUS:1842780106

SP - 212

EP - 215

T2 - 7th International Symposium on IC Technology, Systems and Applications ISIC 97

Y2 - 10 September 1997 through 12 September 1997

ER -

Logic testing of switch-level faults for CMOS unate networks

Abstract

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All Science Journal Classification (ASJC) codes

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