This paper presents an error compensation technique to design a high-speed floating- point special function unit (SFU) based on Taylor series approximation. We develop an iterative algorithm to set the interval endpoints and the corresponding correction values. With the error compensation lookup table (LUT), the total memory size are reduced to only 59.6 Kbyte. Experimental results show the computation gate counts increase slightly. The proposed scheme is modeled in VerilogHDL and synthesized in 180nm CMOS technology after verification.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering