Low complexity and high throughput VLSI architecture for AVC/H.264 CAVLC decoding

Giun Lee Gwo, Chia Cheng Lo, Yuan Ching Chen, Sheau Fang Lei, He Yuan Lin, Ming Jiun Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper introduces a low complexity VLSI hardware architecture for entropy coding with increased throughput, based on the study of the statistical properties of the Context-based Adaptive Variable Length Coding (CAVLC) in AVC/H.264. These enhanced designs are due to the results of the statistical analyses, in which better symbol length prediction was achieved by breaking the recursive dependency among codewords for multi-symbol decoder implementation. The proposed CAVLC decoder can also easily meet real-time requirements for High Definition (HD) (1920x1080) applications, while the clock speed is operated only at 13 MHz under the best case scenario.

Original languageEnglish
Title of host publication2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Pages1229-1232
Number of pages4
DOIs
Publication statusPublished - 2009
Event2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, Taiwan
Duration: 2009 May 242009 May 27

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

Other2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
CountryTaiwan
CityTaipei
Period09-05-2409-05-27

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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