Low complexity and high throughput VLSI architecture for AVC/H.264 CAVLC decoding

Giun Lee Gwo; Chia Cheng Lo; Yuan Ching Chen; Sheau Fang Lei; He Yuan Lin; Ming Jiun Wang

doi:10.1109/ISCAS.2009.5117984

Low complexity and high throughput VLSI architecture for AVC/H.264 CAVLC decoding

Giun Lee Gwo
, Chia Cheng Lo
, Yuan Ching Chen
, Sheau Fang Lei
, He Yuan Lin
, Ming Jiun Wang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

This paper introduces a low complexity VLSI hardware architecture for entropy coding with increased throughput, based on the study of the statistical properties of the Context-based Adaptive Variable Length Coding (CAVLC) in AVC/H.264. These enhanced designs are due to the results of the statistical analyses, in which better symbol length prediction was achieved by breaking the recursive dependency among codewords for multi-symbol decoder implementation. The proposed CAVLC decoder can also easily meet real-time requirements for High Definition (HD) (1920x1080) applications, while the clock speed is operated only at 13 MHz under the best case scenario.

Original language	English
Title of host publication	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Pages	1229-1232
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2009.5117984
Publication status	Published - 2009
Event	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, Taiwan Duration: 2009 May 24 → 2009 May 27

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Other

Other	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Country/Territory	Taiwan
City	Taipei
Period	09-05-24 → 09-05-27

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2009.5117984

Cite this

Gwo, G. L., Lo, C. C., Chen, Y. C., Lei, S. F., Lin, H. Y., & Wang, M. J. (2009). Low complexity and high throughput VLSI architecture for AVC/H.264 CAVLC decoding. In 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 (pp. 1229-1232). Article 5117984 (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2009.5117984

@inproceedings{67485b2fc0ae40f190df795dc57dcf2a,

title = "Low complexity and high throughput VLSI architecture for AVC/H.264 CAVLC decoding",

abstract = "This paper introduces a low complexity VLSI hardware architecture for entropy coding with increased throughput, based on the study of the statistical properties of the Context-based Adaptive Variable Length Coding (CAVLC) in AVC/H.264. These enhanced designs are due to the results of the statistical analyses, in which better symbol length prediction was achieved by breaking the recursive dependency among codewords for multi-symbol decoder implementation. The proposed CAVLC decoder can also easily meet real-time requirements for High Definition (HD) (1920x1080) applications, while the clock speed is operated only at 13 MHz under the best case scenario.",

author = "Gwo, \{Giun Lee\} and Lo, \{Chia Cheng\} and Chen, \{Yuan Ching\} and Lei, \{Sheau Fang\} and Lin, \{He Yuan\} and Wang, \{Ming Jiun\}",

year = "2009",

doi = "10.1109/ISCAS.2009.5117984",

language = "English",

isbn = "9781424438280",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

pages = "1229--1232",

booktitle = "2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009",

note = "2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 ; Conference date: 24-05-2009 Through 27-05-2009",

}

Gwo, GL, Lo, CC, Chen, YC, Lei, SF, Lin, HY & Wang, MJ 2009, Low complexity and high throughput VLSI architecture for AVC/H.264 CAVLC decoding. in 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009., 5117984, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 1229-1232, 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009, Taipei, Taiwan, 09-05-24. https://doi.org/10.1109/ISCAS.2009.5117984

Low complexity and high throughput VLSI architecture for AVC/H.264 CAVLC decoding. / Gwo, Giun Lee; Lo, Chia Cheng; Chen, Yuan Ching et al.
2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009. 2009. p. 1229-1232 5117984 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

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AU - Lo, Chia Cheng

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AB - This paper introduces a low complexity VLSI hardware architecture for entropy coding with increased throughput, based on the study of the statistical properties of the Context-based Adaptive Variable Length Coding (CAVLC) in AVC/H.264. These enhanced designs are due to the results of the statistical analyses, in which better symbol length prediction was achieved by breaking the recursive dependency among codewords for multi-symbol decoder implementation. The proposed CAVLC decoder can also easily meet real-time requirements for High Definition (HD) (1920x1080) applications, while the clock speed is operated only at 13 MHz under the best case scenario.

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M3 - Conference contribution

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SN - 9781424438280

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BT - 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009

T2 - 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009

Y2 - 24 May 2009 through 27 May 2009

ER -

Low complexity and high throughput VLSI architecture for AVC/H.264 CAVLC decoding

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