Abstract
Soft-decision decoding of Reed-Solomon (RS) codes can achieve good coding gain by using the probability information from the channel. Among various soft-decision algorithms, the Chase algorithm has moderate performance and rational complexity and hence is usually designed for hardware implementation. Chase-type decoders, however, still have much higher complexity than that of conventional hard-decision decoders. This paper proposes a reduced-complexity Chase (RCC) algorithm and its corresponding high-speed VLSI architecture. With the developed fast and efficient decision-making scheme, the resulting hardware complexity is greatly reduced while keeping the error correction performance comparable to that of the Chase decoders. For a (255, 239) RS code, experimental results show that the proposed decoder design has at least 44.6% improvement in area-time complexity as compared to the related works.
| Original language | English |
|---|---|
| Title of host publication | Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 |
| Publisher | IEEE Computer Society |
| ISBN (Print) | 9781479927760 |
| DOIs | |
| Publication status | Published - 2014 Jan 1 |
| Event | 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 - Hsinchu, Taiwan Duration: 2014 Apr 28 → 2014 Apr 30 |
Publication series
| Name | Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 |
|---|
Other
| Other | 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 |
|---|---|
| Country | Taiwan |
| City | Hsinchu |
| Period | 14-04-28 → 14-04-30 |
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All Science Journal Classification (ASJC) codes
- Control and Systems Engineering
Cite this
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Low-complexity architecture for Chase soft-decision Reed-Solomon decoding. / Lu, Yung Kuei; Chung, Shen Ming; Shieh, Ming-Der.
Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014. IEEE Computer Society, 2014. 6834896 (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Low-complexity architecture for Chase soft-decision Reed-Solomon decoding
AU - Lu, Yung Kuei
AU - Chung, Shen Ming
AU - Shieh, Ming-Der
PY - 2014/1/1
Y1 - 2014/1/1
N2 - Soft-decision decoding of Reed-Solomon (RS) codes can achieve good coding gain by using the probability information from the channel. Among various soft-decision algorithms, the Chase algorithm has moderate performance and rational complexity and hence is usually designed for hardware implementation. Chase-type decoders, however, still have much higher complexity than that of conventional hard-decision decoders. This paper proposes a reduced-complexity Chase (RCC) algorithm and its corresponding high-speed VLSI architecture. With the developed fast and efficient decision-making scheme, the resulting hardware complexity is greatly reduced while keeping the error correction performance comparable to that of the Chase decoders. For a (255, 239) RS code, experimental results show that the proposed decoder design has at least 44.6% improvement in area-time complexity as compared to the related works.
AB - Soft-decision decoding of Reed-Solomon (RS) codes can achieve good coding gain by using the probability information from the channel. Among various soft-decision algorithms, the Chase algorithm has moderate performance and rational complexity and hence is usually designed for hardware implementation. Chase-type decoders, however, still have much higher complexity than that of conventional hard-decision decoders. This paper proposes a reduced-complexity Chase (RCC) algorithm and its corresponding high-speed VLSI architecture. With the developed fast and efficient decision-making scheme, the resulting hardware complexity is greatly reduced while keeping the error correction performance comparable to that of the Chase decoders. For a (255, 239) RS code, experimental results show that the proposed decoder design has at least 44.6% improvement in area-time complexity as compared to the related works.
UR - http://www.scopus.com/inward/record.url?scp=84903977504&partnerID=8YFLogxK
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U2 - 10.1109/VLSI-DAT.2014.6834896
DO - 10.1109/VLSI-DAT.2014.6834896
M3 - Conference contribution
SN - 9781479927760
T3 - Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
BT - Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
PB - IEEE Computer Society
ER -