Low-cost error tolerance scheme for 3-D CMOS imagers

Hsiu Ming Chang Chang, Jiun Lang Huang, Ding Ming Kwai, Kwang Ting Cheng, Cheng Wen Wu

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)


This paper presents an error tolerance scheme for 3-D CMOS imagers that are constructed by stacking a pixel array of imager sensors, an analog-to-digital converter (ADC) array, and an image signal processor (ISP) array using microbumps (μbumps) and through silicon vias (TSVs). To deliver high-quality images in the presence of single or multiple μbump, ADC, or TSV failures, we propose to interleave the connections from pixels to ADCs and recover the corrupted data in the ISPs. Key design parameters, such as the interleaving stride and the grouping ratio are determined by analyzing the employed error correction algorithm. Architectural simulation results demonstrate that the error tolerance scheme enhances the effective yield of an exemplar 3-D imager from 44% to 97%.

Original languageEnglish
Article number6186837
Pages (from-to)465-474
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number3
Publication statusPublished - 2013 Jan 1

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


Dive into the research topics of 'Low-cost error tolerance scheme for 3-D CMOS imagers'. Together they form a unique fingerprint.

Cite this