Abstract
Several efficient CMOS two-input exclusive-OR (XOR) logic structures have been reported in the past. Based on these XOR gates, we propose two multiple-input XOR circuit configurations, which are smaller, faster, and run at a lower power level than conventional structures formed by directly connecting two-input XOR gates. For exclusive-OR sum-of-products circuits, four transistors can be saved for each product term.
| Original language | English |
|---|---|
| Pages (from-to) | 307-310 |
| Number of pages | 4 |
| Journal | Proceedings of the Annual IEEE International ASIC Conference and Exhibit |
| Publication status | Published - 1995 Dec 1 |
| Event | Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit - Austin, TX, USA Duration: 1995 Sept 18 → 1995 Sept 22 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering