Abstract
This paper presents an architecture for 2-D image decomposition of discrete wavelet transform. In order to avoid the memory transpose problem, we use non-separable approach instead of separable one. Besides, based on the input data reuse concept, a parallel-pipelined architecture is proposed. The main characteristics of this architecture include : (1) needless memory transposition; (2) lower hardware cost; (3) shorter latency; (4) suitable VLSI implementation. Finally, all components in our architecture are simulated based on the accuracy requirement and realized as a single chip physically.
| Original language | English |
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| Pages | 1217-1220 |
| Number of pages | 4 |
| Publication status | Published - 1997 Dec 1 |
| Event | Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2) - Sacramento, CA, USA Duration: 1997 Aug 3 → 1997 Aug 6 |
Other
| Other | Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2) |
|---|---|
| City | Sacramento, CA, USA |
| Period | 97-08-03 → 97-08-06 |
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
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Sheu, M. H., Shieh, M-D., & Liu, S. W. (1997). Low-cost VLSI architecture design for non-separable 2-D Discrete Wavelet Transform. 1217-1220. Paper presented at Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2), Sacramento, CA, USA, .