@inproceedings{78e312c71f0c4997a4069800fb440caf,
title = "Low Latency Design of Polar Decoder for Flash Memory",
abstract = "We propose a multiple error correction coding scheme with systematic polar code to enhance the data reliability and to prolong the endurance for flash memory. A line-based 2-bit simplified successive cancellation (SSC) decoder is integrated with a bit-permutation construction to lower the latency. The patterns of information bits and frozen bits are rearranged. The experimental results show that the hardware implementation of the SSC decoder with the codeword permutation speed up 8.1% compared to the prior design. ",
author = "Tseng, {Yi Fu} and Shieh, {Ming Der} and Kuo, {Chih Hung}",
note = "Funding Information: This work was supported in part by the Ministry of Science and Technology of Taiwan under Grant MOST 109-2221-E-006-197. Publisher Copyright: {\textcopyright} 2021 IEEE.; 8th IEEE International Conference on Consumer Electronics-Taiwan, ICCE-TW 2021 ; Conference date: 15-09-2021 Through 17-09-2021",
year = "2021",
doi = "10.1109/ICCE-TW52618.2021.9603225",
language = "English",
series = "2021 IEEE International Conference on Consumer Electronics-Taiwan, ICCE-TW 2021",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2021 IEEE International Conference on Consumer Electronics-Taiwan, ICCE-TW 2021",
address = "United States",
}