Low Latency Design of Polar Decoder for Flash Memory

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We propose a multiple error correction coding scheme with systematic polar code to enhance the data reliability and to prolong the endurance for flash memory. A line-based 2-bit simplified successive cancellation (SSC) decoder is integrated with a bit-permutation construction to lower the latency. The patterns of information bits and frozen bits are rearranged. The experimental results show that the hardware implementation of the SSC decoder with the codeword permutation speed up 8.1% compared to the prior design.

Original languageEnglish
Title of host publication2021 IEEE International Conference on Consumer Electronics-Taiwan, ICCE-TW 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665433280
DOIs
Publication statusPublished - 2021
Event8th IEEE International Conference on Consumer Electronics-Taiwan, ICCE-TW 2021 - Penghu, Taiwan
Duration: 2021 Sept 152021 Sept 17

Publication series

Name2021 IEEE International Conference on Consumer Electronics-Taiwan, ICCE-TW 2021

Conference

Conference8th IEEE International Conference on Consumer Electronics-Taiwan, ICCE-TW 2021
Country/TerritoryTaiwan
CityPenghu
Period21-09-1521-09-17

All Science Journal Classification (ASJC) codes

  • Artificial Intelligence
  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Control and Optimization
  • Instrumentation

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