Low-Leakage Capacitive Coupling Structure for a-Si:H Gate Driver with Less Delay of Clock Signals Used in AMLCDs

Ming Yang Deng, Wei Sheng Liao, Sung Chun Chen, Jui Hung Chang, Chia En Wu, Chih Lung Lin

Research output: Contribution to journalArticle

Abstract

This work proposes a hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) gate driver with a low-leakage capacitive coupling structure to reduce the delay of the clock signal. The proposed circuit suppresses the fluctuation in the gate node of the driving TFT induced by clock-feed-through effect, reducing the leakage current that flows from the clock signal line to the power source line with a low voltage level. This reduction in the leakage current can improve the degradation in the voltage of the clock signal and thus avoid the increase in the rising time of the scan pulse. Measurements for extracting the drain current versus gate-to-source voltage (ID - VGS) curves of a fabricated a-Si:H TFT are made to establish a simulation TFT model by fitting the obtained curves. For the same parameters of the TFTs and capacitances, the leakage current and the rising time of the output waveform of the proposed circuit are 45.45% and 21.36% lower, respectively, than those of previously developed gate driver.

Original languageEnglish
Article number9032101
Pages (from-to)302-307
Number of pages6
JournalIEEE Journal of the Electron Devices Society
Volume8
DOIs
Publication statusPublished - 2020 Jan 1

All Science Journal Classification (ASJC) codes

  • Biotechnology
  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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