Low overhead design for programmable logic array with testability

K. C. Wei; J. J. Sheu; B. D. Liu

doi:10.1080/00207219408926053

Low overhead design for programmable logic array with testability

K. C. Wei, J. J. Sheu, B. D. Liu

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

A new design to reduce the overhead required for a fully testable PLA is proposed. This design rearranges and groups the product lines into partitions. Then, one extra output line per partition is added to make the whole PLA testable. The silicon area overhead required by this design is significantly less than those of previous methods.

Original language	English
Pages (from-to)	241-250
Number of pages	10
Journal	International Journal of Electronics
Volume	77
Issue number	2
DOIs	https://doi.org/10.1080/00207219408926053
Publication status	Published - 1994 Aug

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1080/00207219408926053

Cite this

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title = "Low overhead design for programmable logic array with testability",

abstract = "A new design to reduce the overhead required for a fully testable PLA is proposed. This design rearranges and groups the product lines into partitions. Then, one extra output line per partition is added to make the whole PLA testable. The silicon area overhead required by this design is significantly less than those of previous methods.",

author = "Wei, {K. C.} and Sheu, {J. J.} and Liu, {B. D.}",

note = "Funding Information: The work was supported by the National Science Council, Republic of China under Contract No. NSC8 1 -0404-E-006-116.",

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Low overhead design for programmable logic array with testability

Abstract

All Science Journal Classification (ASJC) codes

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