Low-power circuit techniques for low-voltage pipelined ADCs based on switched-opamp architecture

Hsin Hung Ou, Soon Jyh Chang, Bin Da Liu

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)

Abstract

This paper proposes useful circuit structures for achieving a low-voltage/low-power pipelined ADC based on switched-opamp architecture. First, a novel unity-feedback-factor sample-and-hold which manipulates the features of switched-opamp technique is presented. Second, opamp-sharing is merged into switched-opamp structure with a proposed dual-output opamp configuration. A 0.8-V, 9-bit, 10-Msample/s pipelined ADC is designed to verify the proposed circuit. Simulation results using a 0.18-μm CMOS 1P6M process demonstrate the figure-of-merit of this pipelined ADC is only 0.71 pJ/step.

Original languageEnglish
Pages (from-to)461-468
Number of pages8
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE91-A
Issue number2
DOIs
Publication statusPublished - 2008

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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