H.264/AVC achieves a higher compression ratio than previous standards. However, this standard is also more complex because of the use of methods such as context-based adaptive binary arithmetic coding (CABAC). The high computational complexity of CABAC results in large power consumption. This study presents a systematic analysis for designing a low-power architecture which includes an embedded cache. The analysis provides the mapping scheme between the cache and the main memory where the contexts are stored. The observations for the proposed scheme are based on the statistical correlation between neighbouring blocks for H.264 coding. The proposed scheme allows the context access operations to hit frequently in the cache, significantly reducing the power consumption. The proposed architecture lowers power consumption by up to 50% compared to designs without embedded cache. An efficient bit-packing method of output bitstream that can be implemented by pipeline structure for high encoding data throughput is also proposed. The throughput of the proposed design is up to 200 Mbins per second for H.264 main profile.
All Science Journal Classification (ASJC) codes
- Signal Processing
- Computer Vision and Pattern Recognition
- Electrical and Electronic Engineering