Low power design of H.264 CAVLC decoder

Heng Yao Lin, Ying Hong Lu, Bin Da Liu, Jar Ferr Yang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

23 Citations (Scopus)

Abstract

In this paper, a low power architecture for realizing the CAVLC decoder is proposed. In traditional VLC decoding algorithms, we could search a level in Huffman coding tree per operation. Therefore, the throughput rate is limited by the searching level. The CAVLC algorithm takes the advantage of the trend among AC coefficients in each block to predict the next codeword. The prediction mechanism can significantly improve the decoding efficiency. Hence, we suggested two efficient approaches, table partitioning and prefix predecoding, to reduce the power consumption in decoding the VLC codes. The proposed low-power CAVLD architecture achieves the real-time requirement for 720p HD (1280×720) format, while the clock is operated at 125 MHz. In simulations, the proposed architecture can reduce about 25% of power consumption in comparison to its counterpart without low power design.

Original languageEnglish
Title of host publicationISCAS 2006
Subtitle of host publication2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages2689-2692
Number of pages4
Publication statusPublished - 2006 Dec 1
EventISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece
Duration: 2006 May 212006 May 24

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

OtherISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Country/TerritoryGreece
CityKos
Period06-05-2106-05-24

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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