TY - GEN
T1 - Low power design of H.264 CAVLC decoder
AU - Lin, Heng Yao
AU - Lu, Ying Hong
AU - Liu, Bin Da
AU - Yang, Jar Ferr
PY - 2006/12/1
Y1 - 2006/12/1
N2 - In this paper, a low power architecture for realizing the CAVLC decoder is proposed. In traditional VLC decoding algorithms, we could search a level in Huffman coding tree per operation. Therefore, the throughput rate is limited by the searching level. The CAVLC algorithm takes the advantage of the trend among AC coefficients in each block to predict the next codeword. The prediction mechanism can significantly improve the decoding efficiency. Hence, we suggested two efficient approaches, table partitioning and prefix predecoding, to reduce the power consumption in decoding the VLC codes. The proposed low-power CAVLD architecture achieves the real-time requirement for 720p HD (1280×720) format, while the clock is operated at 125 MHz. In simulations, the proposed architecture can reduce about 25% of power consumption in comparison to its counterpart without low power design.
AB - In this paper, a low power architecture for realizing the CAVLC decoder is proposed. In traditional VLC decoding algorithms, we could search a level in Huffman coding tree per operation. Therefore, the throughput rate is limited by the searching level. The CAVLC algorithm takes the advantage of the trend among AC coefficients in each block to predict the next codeword. The prediction mechanism can significantly improve the decoding efficiency. Hence, we suggested two efficient approaches, table partitioning and prefix predecoding, to reduce the power consumption in decoding the VLC codes. The proposed low-power CAVLD architecture achieves the real-time requirement for 720p HD (1280×720) format, while the clock is operated at 125 MHz. In simulations, the proposed architecture can reduce about 25% of power consumption in comparison to its counterpart without low power design.
UR - http://www.scopus.com/inward/record.url?scp=34247270435&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=34247270435&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:34247270435
SN - 0780393902
SN - 9780780393905
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 2689
EP - 2692
BT - ISCAS 2006
T2 - ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Y2 - 21 May 2006 through 24 May 2006
ER -