Low power design of phase-change memory based on a comprehensive model

M. H. Chiang, Y. B. Liao, J. T. Lin, W. C. Hsu, C. Yu, P. C. Chiang, Y. Y. Hsu, W. H. Liu, S. S. Sheu, K. Li Su, M. J. Kao, M. J. Tsai

Research output: Contribution to journalArticle

Abstract

In this study, the authors propose non-conventional phase-change memory programming schemes using a comprehensive model, which integrates the underlying electrical and thermal theories. Various pulsing schemes aiming to reduce operation power without compromising performance are assessed based on a calibrated model. Our results suggest that optimisation of power consumption can be done simply by design of pulsing techniques.

Original languageEnglish
Article numberICDTA6000004000004000285000001
Pages (from-to)285-292
Number of pages8
JournalIET Computers and Digital Techniques
Volume4
Issue number4
DOIs
Publication statusPublished - 2010 Jul 1

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Chiang, M. H., Liao, Y. B., Lin, J. T., Hsu, W. C., Yu, C., Chiang, P. C., Hsu, Y. Y., Liu, W. H., Sheu, S. S., Su, K. L., Kao, M. J., & Tsai, M. J. (2010). Low power design of phase-change memory based on a comprehensive model. IET Computers and Digital Techniques, 4(4), 285-292. [ICDTA6000004000004000285000001]. https://doi.org/10.1049/iet-cdt.2009.0037