Low power pipelined SAR ADC with loading-free architecture

Jia Jhang Wu; Soon Jyh Chang; Sheng Hsiung Lin; Chun Po Huang; Guan Ying Huang

doi:10.1109/VLSI-DAT.2014.6834906

Low power pipelined SAR ADC with loading-free architecture

Jia Jhang Wu, Soon Jyh Chang, Sheng Hsiung Lin, Chun Po Huang, Guan Ying Huang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper presents a 12-bit 70-MS/s pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with loading-free architecture. This work proposes a loading-free concept of merging the feedback capacitor and the capacitor array of the second-stage SAR ADC to reduce op-amp output loading and area. In addition, the fixed-window function technique is used to reduce the power consumption and tolerate non-idealities in the first-stage SAR ADC. The ADC core occupies an active area of 0.117 mm² in TSMC 90-nm 1P9M CMOS process. The measured results shows that the proposed ADC achieves 55.98 dB SNDR with 2.72 mW power consumption at 1 MHz input frequency.

Original language	English
Title of host publication	Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
Publisher	IEEE Computer Society
ISBN (Print)	9781479927760
DOIs	https://doi.org/10.1109/VLSI-DAT.2014.6834906
Publication status	Published - 2014 Jan 1
Event	2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 - Hsinchu, Taiwan Duration: 2014 Apr 28 → 2014 Apr 30

Publication series

Name	Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014

Other

Other	2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
Country	Taiwan
City	Hsinchu
Period	14-04-28 → 14-04-30

All Science Journal Classification (ASJC) codes

Control and Systems Engineering

Access to Document

10.1109/VLSI-DAT.2014.6834906

Fingerprint Dive into the research topics of 'Low power pipelined SAR ADC with loading-free architecture'. Together they form a unique fingerprint.

Cite this

Wu, J. J., Chang, S. J., Lin, S. H., Huang, C. P., & Huang, G. Y. (2014). Low power pipelined SAR ADC with loading-free architecture. In Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 [6834906] (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014). IEEE Computer Society. https://doi.org/10.1109/VLSI-DAT.2014.6834906

Wu, Jia Jhang ; Chang, Soon Jyh ; Lin, Sheng Hsiung ; Huang, Chun Po ; Huang, Guan Ying. / Low power pipelined SAR ADC with loading-free architecture. Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014. IEEE Computer Society, 2014. (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014).

@inproceedings{0b61f1f9c8e741d79d1ffb9437be3bc7,

title = "Low power pipelined SAR ADC with loading-free architecture",

abstract = "This paper presents a 12-bit 70-MS/s pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with loading-free architecture. This work proposes a loading-free concept of merging the feedback capacitor and the capacitor array of the second-stage SAR ADC to reduce op-amp output loading and area. In addition, the fixed-window function technique is used to reduce the power consumption and tolerate non-idealities in the first-stage SAR ADC. The ADC core occupies an active area of 0.117 mm2 in TSMC 90-nm 1P9M CMOS process. The measured results shows that the proposed ADC achieves 55.98 dB SNDR with 2.72 mW power consumption at 1 MHz input frequency.",

author = "Wu, {Jia Jhang} and Chang, {Soon Jyh} and Lin, {Sheng Hsiung} and Huang, {Chun Po} and Huang, {Guan Ying}",

year = "2014",

month = jan,

day = "1",

doi = "10.1109/VLSI-DAT.2014.6834906",

language = "English",

isbn = "9781479927760",

series = "Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014",

publisher = "IEEE Computer Society",

booktitle = "Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014",

address = "United States",

note = "2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 ; Conference date: 28-04-2014 Through 30-04-2014",

}

Wu, JJ, Chang, SJ, Lin, SH, Huang, CP & Huang, GY 2014, Low power pipelined SAR ADC with loading-free architecture. in Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014., 6834906, Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014, IEEE Computer Society, 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014, Hsinchu, Taiwan, 14-04-28. https://doi.org/10.1109/VLSI-DAT.2014.6834906

Low power pipelined SAR ADC with loading-free architecture. / Wu, Jia Jhang; Chang, Soon Jyh; Lin, Sheng Hsiung; Huang, Chun Po; Huang, Guan Ying.

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014. IEEE Computer Society, 2014. 6834906 (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Low power pipelined SAR ADC with loading-free architecture

AU - Wu, Jia Jhang

AU - Chang, Soon Jyh

AU - Lin, Sheng Hsiung

AU - Huang, Chun Po

AU - Huang, Guan Ying

PY - 2014/1/1

Y1 - 2014/1/1

N2 - This paper presents a 12-bit 70-MS/s pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with loading-free architecture. This work proposes a loading-free concept of merging the feedback capacitor and the capacitor array of the second-stage SAR ADC to reduce op-amp output loading and area. In addition, the fixed-window function technique is used to reduce the power consumption and tolerate non-idealities in the first-stage SAR ADC. The ADC core occupies an active area of 0.117 mm2 in TSMC 90-nm 1P9M CMOS process. The measured results shows that the proposed ADC achieves 55.98 dB SNDR with 2.72 mW power consumption at 1 MHz input frequency.

AB - This paper presents a 12-bit 70-MS/s pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with loading-free architecture. This work proposes a loading-free concept of merging the feedback capacitor and the capacitor array of the second-stage SAR ADC to reduce op-amp output loading and area. In addition, the fixed-window function technique is used to reduce the power consumption and tolerate non-idealities in the first-stage SAR ADC. The ADC core occupies an active area of 0.117 mm2 in TSMC 90-nm 1P9M CMOS process. The measured results shows that the proposed ADC achieves 55.98 dB SNDR with 2.72 mW power consumption at 1 MHz input frequency.

UR - http://www.scopus.com/inward/record.url?scp=84903978355&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84903978355&partnerID=8YFLogxK

U2 - 10.1109/VLSI-DAT.2014.6834906

DO - 10.1109/VLSI-DAT.2014.6834906

M3 - Conference contribution

AN - SCOPUS:84903978355

SN - 9781479927760

T3 - Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014

BT - Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014

PB - IEEE Computer Society

T2 - 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014

Y2 - 28 April 2014 through 30 April 2014

ER -

Wu JJ, Chang SJ, Lin SH, Huang CP, Huang GY. Low power pipelined SAR ADC with loading-free architecture. In Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014. IEEE Computer Society. 2014. 6834906. (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014). https://doi.org/10.1109/VLSI-DAT.2014.6834906