@inproceedings{0b61f1f9c8e741d79d1ffb9437be3bc7,
title = "Low power pipelined SAR ADC with loading-free architecture",
abstract = "This paper presents a 12-bit 70-MS/s pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with loading-free architecture. This work proposes a loading-free concept of merging the feedback capacitor and the capacitor array of the second-stage SAR ADC to reduce op-amp output loading and area. In addition, the fixed-window function technique is used to reduce the power consumption and tolerate non-idealities in the first-stage SAR ADC. The ADC core occupies an active area of 0.117 mm2 in TSMC 90-nm 1P9M CMOS process. The measured results shows that the proposed ADC achieves 55.98 dB SNDR with 2.72 mW power consumption at 1 MHz input frequency.",
author = "Wu, {Jia Jhang} and Chang, {Soon Jyh} and Lin, {Sheng Hsiung} and Huang, {Chun Po} and Huang, {Guan Ying}",
year = "2014",
month = jan,
day = "1",
doi = "10.1109/VLSI-DAT.2014.6834906",
language = "English",
isbn = "9781479927760",
series = "Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014",
publisher = "IEEE Computer Society",
booktitle = "Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014",
address = "United States",
note = "2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 ; Conference date: 28-04-2014 Through 30-04-2014",
}