Low power pipelined SAR ADC with loading-free architecture

Jia Jhang Wu, Soon Jyh Chang, Sheng Hsiung Lin, Chun Po Huang, Guan Ying Huang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents a 12-bit 70-MS/s pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with loading-free architecture. This work proposes a loading-free concept of merging the feedback capacitor and the capacitor array of the second-stage SAR ADC to reduce op-amp output loading and area. In addition, the fixed-window function technique is used to reduce the power consumption and tolerate non-idealities in the first-stage SAR ADC. The ADC core occupies an active area of 0.117 mm2 in TSMC 90-nm 1P9M CMOS process. The measured results shows that the proposed ADC achieves 55.98 dB SNDR with 2.72 mW power consumption at 1 MHz input frequency.

Original languageEnglish
Title of host publicationTechnical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
PublisherIEEE Computer Society
ISBN (Print)9781479927760
DOIs
Publication statusPublished - 2014 Jan 1
Event2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 - Hsinchu, Taiwan
Duration: 2014 Apr 282014 Apr 30

Publication series

NameTechnical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014

Other

Other2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
CountryTaiwan
CityHsinchu
Period14-04-2814-04-30

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering

Fingerprint Dive into the research topics of 'Low power pipelined SAR ADC with loading-free architecture'. Together they form a unique fingerprint.

Cite this