Low-power testing for C-testable iterative logic arrays

Shih Arn Hwang, Cheng Wen Wu

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Abstract

Deterministic test patterns often lead to much larger power consumption than normal input patterns, resulting in higher tester requirement and testing cost. We show that, without affecting the test quality, the most power-efficient test set for C-testable iterative logic arrays can be obtained. The proposed method takes only polynomial time with respect to the cell size, and is independent of the array size.

Original languageEnglish
Pages355-358
Number of pages4
Publication statusPublished - 1997 Jan 1
EventProceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications - Taipei, China
Duration: 1997 Jun 31997 Jun 5

Other

OtherProceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications
CityTaipei, China
Period97-06-0397-06-05

Fingerprint

Electric power utilization
Polynomials
Testing
Costs

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Hwang, S. A., & Wu, C. W. (1997). Low-power testing for C-testable iterative logic arrays. 355-358. Paper presented at Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications, Taipei, China, .
Hwang, Shih Arn ; Wu, Cheng Wen. / Low-power testing for C-testable iterative logic arrays. Paper presented at Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications, Taipei, China, .4 p.
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Hwang, SA & Wu, CW 1997, 'Low-power testing for C-testable iterative logic arrays', Paper presented at Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications, Taipei, China, 97-06-03 - 97-06-05 pp. 355-358.

Low-power testing for C-testable iterative logic arrays. / Hwang, Shih Arn; Wu, Cheng Wen.

1997. 355-358 Paper presented at Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications, Taipei, China, .

Research output: Contribution to conferencePaper

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N2 - Deterministic test patterns often lead to much larger power consumption than normal input patterns, resulting in higher tester requirement and testing cost. We show that, without affecting the test quality, the most power-efficient test set for C-testable iterative logic arrays can be obtained. The proposed method takes only polynomial time with respect to the cell size, and is independent of the array size.

AB - Deterministic test patterns often lead to much larger power consumption than normal input patterns, resulting in higher tester requirement and testing cost. We show that, without affecting the test quality, the most power-efficient test set for C-testable iterative logic arrays can be obtained. The proposed method takes only polynomial time with respect to the cell size, and is independent of the array size.

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Hwang SA, Wu CW. Low-power testing for C-testable iterative logic arrays. 1997. Paper presented at Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications, Taipei, China, .