Low-Power Testing for C-testable Iterative Logic Arrays

S.-A. Hwang, Cheng-Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Original languageEnglish
Title of host publicationIEEE International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA)
Place of PublicationTaipei
Pages355-358
Publication statusPublished - 1997 Jun

Cite this

Hwang, S-A., & Wu, C-W. (1997). Low-Power Testing for C-testable Iterative Logic Arrays. In IEEE International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA) (pp. 355-358).