Low-power VLSI architecture for the Viterbi decoder

Wann Shyang Ju, Ming Der Shieh, Ming Hwa Sheu

Research output: Contribution to conferencePaper

2 Citations (Scopus)

Abstract

This paper presents a VLSI architecture for the Viterbi decoder toward reducing average power dissipation based on the modified T-algorithm and the radix-2 butterfly module. Simulation results show that on the average, more than half of states at each time stage are not needed to be processed for the (4,1,6) convolutional code at bit error probability Pb≤10-2. Therefore, significant power reduction can be achieved by reducing the total number of path metric computations and eliminating waste memory read/write operations. Based on the TSMC 0.6 um SPDM process and the Compass cell library, the resulting core size is 2761*2996 um2.

Original languageEnglish
Pages1201-1204
Number of pages4
Publication statusPublished - 1997 Dec 1
EventProceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2) - Sacramento, CA, USA
Duration: 1997 Aug 31997 Aug 6

Other

OtherProceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2)
CitySacramento, CA, USA
Period97-08-0397-08-06

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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  • Cite this

    Ju, W. S., Shieh, M. D., & Sheu, M. H. (1997). Low-power VLSI architecture for the Viterbi decoder. 1201-1204. Paper presented at Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2), Sacramento, CA, USA, .