Low temperature post-annealing of ZnO thin-film transistors with high-k gate dielectrics

Henry J.H. Chen, Barry B.L. Yeh, Wei-Yang Chou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This work addresses the thin film analysis of ZnO and electrical characteristics of ZnO TFTs with HfO2 high-k: gate dielectrics after low temperature post-annealing. The SIMS analysis shows that the diffusion of Zn atoms into the HTO2 will occur after 300 °C annealing and the related electrical characteristics indicates that the 200 °C annealing will be the optimized annealing condition for the ZnO/HfO2/ITO based TFTs. The ZnO TFTs after optimized annealing condition exhibited transistor behavior over the range 0-7 V; the field effect mobility, subthreshold slope and on/off ratio were measured to be 1.3 cm2V-1s-1, 0.5 V/decade and ∼106, respectively.

Original languageEnglish
Title of host publicationECS Transactions - Thin Film Transistors 9, TFT 9
Pages315-322
Number of pages8
Edition9
DOIs
Publication statusPublished - 2008 Dec 1
EventThin Film Transistors 9, TFT 9 - 214th ECS Meeting - Honolulu, HI, United States
Duration: 2008 Oct 132008 Oct 16

Publication series

NameECS Transactions
Number9
Volume16
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

OtherThin Film Transistors 9, TFT 9 - 214th ECS Meeting
CountryUnited States
CityHonolulu, HI
Period08-10-1308-10-16

Fingerprint

Gate dielectrics
Thin film transistors
Annealing
Temperature
Secondary ion mass spectrometry
Transistors
Thin films
Atoms

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Chen, H. J. H., Yeh, B. B. L., & Chou, W-Y. (2008). Low temperature post-annealing of ZnO thin-film transistors with high-k gate dielectrics. In ECS Transactions - Thin Film Transistors 9, TFT 9 (9 ed., pp. 315-322). (ECS Transactions; Vol. 16, No. 9). https://doi.org/10.1149/1.2980569
Chen, Henry J.H. ; Yeh, Barry B.L. ; Chou, Wei-Yang. / Low temperature post-annealing of ZnO thin-film transistors with high-k gate dielectrics. ECS Transactions - Thin Film Transistors 9, TFT 9. 9. ed. 2008. pp. 315-322 (ECS Transactions; 9).
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Chen, HJH, Yeh, BBL & Chou, W-Y 2008, Low temperature post-annealing of ZnO thin-film transistors with high-k gate dielectrics. in ECS Transactions - Thin Film Transistors 9, TFT 9. 9 edn, ECS Transactions, no. 9, vol. 16, pp. 315-322, Thin Film Transistors 9, TFT 9 - 214th ECS Meeting, Honolulu, HI, United States, 08-10-13. https://doi.org/10.1149/1.2980569

Low temperature post-annealing of ZnO thin-film transistors with high-k gate dielectrics. / Chen, Henry J.H.; Yeh, Barry B.L.; Chou, Wei-Yang.

ECS Transactions - Thin Film Transistors 9, TFT 9. 9. ed. 2008. p. 315-322 (ECS Transactions; Vol. 16, No. 9).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Chen HJH, Yeh BBL, Chou W-Y. Low temperature post-annealing of ZnO thin-film transistors with high-k gate dielectrics. In ECS Transactions - Thin Film Transistors 9, TFT 9. 9 ed. 2008. p. 315-322. (ECS Transactions; 9). https://doi.org/10.1149/1.2980569