Low test-application time method for EEPLA testing

K. C. Wei; B. D. Liu; J. J. Tang

doi:10.1049/ip-cdt:19970636

Low test-application time method for EEPLA testing

K. C. Wei, B. D. Liu, J. J. Tang

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

An efficient method for EEPLA testing is presented. In this method the authors propose an interleave programming algorithm for the EEPLA to enhance the controllability of the OR plane and the observability of the AND plane during the testing of EEPLA. The salient features of this method are: (i) low overhead, (ii) high fault coverage, (iii) simple test set, and (iv) low test-application time. Using this method, all multiple stuck-at faults, multiple crosspoint faults and all multiple bridging faults can be detected.

Original language	English
Pages (from-to)	39-42
Number of pages	4
Journal	IEE Proceedings: Computers and Digital Techniques
Volume	144
Issue number	1
DOIs	https://doi.org/10.1049/ip-cdt:19970636
Publication status	Published - 1997 Jan 1

All Science Journal Classification (ASJC) codes

Theoretical Computer Science
Hardware and Architecture
Computational Theory and Mathematics

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