Abstract
An efficient method for EEPLA testing is presented. In this method the authors propose an interleave programming algorithm for the EEPLA to enhance the controllability of the OR plane and the observability of the AND plane during the testing of EEPLA. The salient features of this method are: (i) low overhead, (ii) high fault coverage, (iii) simple test set, and (iv) low test-application time. Using this method, all multiple stuck-at faults, multiple crosspoint faults and all multiple bridging faults can be detected.
| Original language | English |
|---|---|
| Pages (from-to) | 39-42 |
| Number of pages | 4 |
| Journal | IEE Proceedings: Computers and Digital Techniques |
| Volume | 144 |
| Issue number | 1 |
| DOIs | |
| Publication status | Published - 1997 Jan 1 |
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All Science Journal Classification (ASJC) codes
- Theoretical Computer Science
- Hardware and Architecture
- Computational Theory and Mathematics
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Low test-application time method for EEPLA testing. / Wei, K. C.; Liu, Bin-Da; Tang, J. J.
In: IEE Proceedings: Computers and Digital Techniques, Vol. 144, No. 1, 01.01.1997, p. 39-42.Research output: Contribution to journal › Article
TY - JOUR
T1 - Low test-application time method for EEPLA testing
AU - Wei, K. C.
AU - Liu, Bin-Da
AU - Tang, J. J.
PY - 1997/1/1
Y1 - 1997/1/1
N2 - An efficient method for EEPLA testing is presented. In this method the authors propose an interleave programming algorithm for the EEPLA to enhance the controllability of the OR plane and the observability of the AND plane during the testing of EEPLA. The salient features of this method are: (i) low overhead, (ii) high fault coverage, (iii) simple test set, and (iv) low test-application time. Using this method, all multiple stuck-at faults, multiple crosspoint faults and all multiple bridging faults can be detected.
AB - An efficient method for EEPLA testing is presented. In this method the authors propose an interleave programming algorithm for the EEPLA to enhance the controllability of the OR plane and the observability of the AND plane during the testing of EEPLA. The salient features of this method are: (i) low overhead, (ii) high fault coverage, (iii) simple test set, and (iv) low test-application time. Using this method, all multiple stuck-at faults, multiple crosspoint faults and all multiple bridging faults can be detected.
UR - http://www.scopus.com/inward/record.url?scp=0030682268&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0030682268&partnerID=8YFLogxK
U2 - 10.1049/ip-cdt:19970636
DO - 10.1049/ip-cdt:19970636
M3 - Article
AN - SCOPUS:0030682268
VL - 144
SP - 39
EP - 42
JO - IEE Proceedings: Computers and Digital Techniques
JF - IEE Proceedings: Computers and Digital Techniques
SN - 1350-2387
IS - 1
ER -