Mechanism and improvement of on-resistance degradation induced by avalanche breakdown in lateral DMOS transistors

Jone F. Chen; J. R. Lee; Kuo Ming Wu; Tsung Yi Huang; C. M. Liu

doi:10.1109/TED.2008.924866

Mechanism and improvement of on-resistance degradation induced by avalanche breakdown in lateral DMOS transistors

Jone F. Chen
, J. R. Lee
, Kuo Ming Wu
, Tsung Yi Huang
, C. M. Liu

Research output: Contribution to journal › Article › peer-review

9 Citations (Scopus)

Abstract

On-resistance (R_on) degradation induced by avalanche breakdown is investigated in lateral double-diffused MOS transistors with different dosages of n-type drain drift (NDD) region. R_on degradation is caused by interface state and positive oxide-trapped charge created near the drain-side polygate edge. The device with a higher NDD dosage generates less interface state but more positive oxide-trapped charge, leading to a reduction in R_on degradation. Such a result reveals that increasing NDD dosage reduces avalanche-breakdown-induced R_on degradation.

Original language	English
Pages (from-to)	2259-2262
Number of pages	4
Journal	IEEE Transactions on Electron Devices
Volume	55
Issue number	8
DOIs	https://doi.org/10.1109/TED.2008.924866
Publication status	Published - 2008

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/TED.2008.924866

Cite this

@article{45d7267ccad0475ba6bc7fbea946c1f4,

title = "Mechanism and improvement of on-resistance degradation induced by avalanche breakdown in lateral DMOS transistors",

abstract = "On-resistance (Ron) degradation induced by avalanche breakdown is investigated in lateral double-diffused MOS transistors with different dosages of n-type drain drift (NDD) region. Ron degradation is caused by interface state and positive oxide-trapped charge created near the drain-side polygate edge. The device with a higher NDD dosage generates less interface state but more positive oxide-trapped charge, leading to a reduction in Ron degradation. Such a result reveals that increasing NDD dosage reduces avalanche-breakdown-induced Ron degradation.",

author = "Chen, \{Jone F.\} and Lee, \{J. R.\} and Wu, \{Kuo Ming\} and Huang, \{Tsung Yi\} and Liu, \{C. M.\}",

year = "2008",

doi = "10.1109/TED.2008.924866",

language = "English",

volume = "55",

pages = "2259--2262",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "8",

}

TY - JOUR

T1 - Mechanism and improvement of on-resistance degradation induced by avalanche breakdown in lateral DMOS transistors

AU - Chen, Jone F.

AU - Lee, J. R.

AU - Wu, Kuo Ming

AU - Huang, Tsung Yi

AU - Liu, C. M.

PY - 2008

Y1 - 2008

N2 - On-resistance (Ron) degradation induced by avalanche breakdown is investigated in lateral double-diffused MOS transistors with different dosages of n-type drain drift (NDD) region. Ron degradation is caused by interface state and positive oxide-trapped charge created near the drain-side polygate edge. The device with a higher NDD dosage generates less interface state but more positive oxide-trapped charge, leading to a reduction in Ron degradation. Such a result reveals that increasing NDD dosage reduces avalanche-breakdown-induced Ron degradation.

AB - On-resistance (Ron) degradation induced by avalanche breakdown is investigated in lateral double-diffused MOS transistors with different dosages of n-type drain drift (NDD) region. Ron degradation is caused by interface state and positive oxide-trapped charge created near the drain-side polygate edge. The device with a higher NDD dosage generates less interface state but more positive oxide-trapped charge, leading to a reduction in Ron degradation. Such a result reveals that increasing NDD dosage reduces avalanche-breakdown-induced Ron degradation.

UR - https://www.scopus.com/pages/publications/49249134570

UR - https://www.scopus.com/pages/publications/49249134570#tab=citedBy

U2 - 10.1109/TED.2008.924866

DO - 10.1109/TED.2008.924866

M3 - Article

AN - SCOPUS:49249134570

SN - 0018-9383

VL - 55

SP - 2259

EP - 2262

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 8

ER -

Mechanism and improvement of on-resistance degradation induced by avalanche breakdown in lateral DMOS transistors

Abstract

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this